JPS5882052U - Tuner output circuit - Google Patents

Tuner output circuit

Info

Publication number
JPS5882052U
JPS5882052U JP17599881U JP17599881U JPS5882052U JP S5882052 U JPS5882052 U JP S5882052U JP 17599881 U JP17599881 U JP 17599881U JP 17599881 U JP17599881 U JP 17599881U JP S5882052 U JPS5882052 U JP S5882052U
Authority
JP
Japan
Prior art keywords
signal
tuner
output circuit
pass filter
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17599881U
Other languages
Japanese (ja)
Other versions
JPS6325783Y2 (en
Inventor
晃三 中田
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP17599881U priority Critical patent/JPS5882052U/en
Publication of JPS5882052U publication Critical patent/JPS5882052U/en
Application granted granted Critical
Publication of JPS6325783Y2 publication Critical patent/JPS6325783Y2/ja
Granted legal-status Critical Current

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  • Filters And Equalizers (AREA)
  • Superheterodyne Receivers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のチューナ出力回路図、及び第２図は本考
案に係るＦＥＴ混合段を含むチューナの出力回路図であ
る。 １・・・・・−ＦＥＴ（混合段）、２・・・・・・ＩＦ
出力端子、１３・・・・・・ＩＦ複同調フィルタ、１４
・・・・・・ローパスフィルタ、２１．２２・・・・・
・脚部コンデンサ、２３・・・・・・中央部インダクタ
、２４・・・・・・抵抗（約５０〜１５０Ω）。FIG. 1 is a conventional tuner output circuit diagram, and FIG. 2 is a tuner output circuit diagram including an FET mixing stage according to the present invention. 1...-FET (mixing stage), 2...IF
Output terminal, 13...IF double tuning filter, 14
...Low pass filter, 21.22...
- Leg capacitor, 23...Central inductor, 24...Resistance (approximately 50 to 150Ω).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＲＦ入力信号とローカル発振信号を混合するＭＯＳ　　
ＦＥＴ混合回路の出力側にＩＦ複同調フィルタとローパ
スフィルタとを配設して出力端子からＩＦ倍信号導出す
るチューナにおいて、前記ローパスフィルタはτ形状回
路の脚部コンデンサと中央部インダクタをそれぞれロー
カル発振信号の高調波を減衰するに充分な値に選定して
構成すると共に前記中央部インダクタに抵抗値が約５０
〜１５０Ωの範囲で選定される抵抗を並列接続したこと
を特徴とするチューナ出力回路。MOS that mixes RF input signal and local oscillation signal
In a tuner in which an IF double-tuned filter and a low-pass filter are disposed on the output side of a FET mixing circuit to derive an IF multiplied signal from the output terminal, the low-pass filter locally oscillates the leg capacitors and central inductor of the τ-shaped circuit, respectively. The center inductor has a resistance value of approximately 50 Ω, and is selected to have a value sufficient to attenuate the harmonics of the signal.
A tuner output circuit characterized in that resistors selected in the range of ~150Ω are connected in parallel.
JP17599881U 1981-11-25 1981-11-25 Tuner output circuit Granted JPS5882052U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17599881U JPS5882052U (en) 1981-11-25 1981-11-25 Tuner output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17599881U JPS5882052U (en) 1981-11-25 1981-11-25 Tuner output circuit

Publications (2)

Publication Number Publication Date
JPS5882052U true JPS5882052U (en) 1983-06-03
JPS6325783Y2 JPS6325783Y2 (en) 1988-07-13

Family

ID=29968651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17599881U Granted JPS5882052U (en) 1981-11-25 1981-11-25 Tuner output circuit

Country Status (1)

Country Link
JP (1) JPS5882052U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017129503A (en) * 2016-01-21 2017-07-27 日本電信電話株式会社 Conduction disturbing wave measurement device
JP2022064322A (en) * 2020-10-13 2022-04-25 マーベル アジア ピーティーイー、リミテッド PARASITIC REDUCTION IN POWER OVER DATA LINE (PoDL) FILTER FOR MULTI-GIGABIT ETHERNET (R)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5020646A (en) * 1973-06-22 1975-03-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5020646A (en) * 1973-06-22 1975-03-05

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017129503A (en) * 2016-01-21 2017-07-27 日本電信電話株式会社 Conduction disturbing wave measurement device
JP2022064322A (en) * 2020-10-13 2022-04-25 マーベル アジア ピーティーイー、リミテッド PARASITIC REDUCTION IN POWER OVER DATA LINE (PoDL) FILTER FOR MULTI-GIGABIT ETHERNET (R)

Also Published As

Publication number Publication date
JPS6325783Y2 (en) 1988-07-13

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