JPS588206U - semiconductor circuit - Google Patents
semiconductor circuitInfo
- Publication number
- JPS588206U JPS588206U JP3460381U JP3460381U JPS588206U JP S588206 U JPS588206 U JP S588206U JP 3460381 U JP3460381 U JP 3460381U JP 3460381 U JP3460381 U JP 3460381U JP S588206 U JPS588206 U JP S588206U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- drain
- emitter
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のトランジスタ回路の接続図、第２図は本
考案の一例の接続図、第３図は本考案の他の例の接続図
、第４図は本考案の説明に供する回路図である。
１は第１のトランジスタ、７は第２のトランジスタ、１
３はバイアス抵抗である。Fig. 1 is a connection diagram of a conventional transistor circuit, Fig. 2 is a connection diagram of an example of the present invention, Fig. 3 is a connection diagram of another example of the present invention, and Fig. 4 is a circuit diagram for explaining the present invention. It is. 1 is the first transistor, 7 is the second transistor, 1
3 is a bias resistor.
Claims (1)
（ドレイン）が電源端子に接続されエミッタ（ソース）
が負荷インピーダンスを介して接地されてそのエミッタ
（ソース）より出力が取り出されるエミッタ（ソース）
フォロア構成の第２□ のトランジスタと、上記第１
のトランジスタのコレクタ（ドレイン）と上記第２のト
ランジスタのベース（ゲート）との間に直流的に接続さ
れたコイルと、上記第２のトランジスタのコレクタ（ド
レイン）とベース（ゲート）との間に直流的に接続され
たバイアス抵抗とよりなり、上記電源端子より上記バイ
アス抵抗を介して上記第２のトランジスタのベース（ゲ
ート）にバイアス電流（電圧）が供給されると共に上記
バイアス抵抗及び上記コイルの直列回路を介して上記第
１のトランジスタにコレクタ（ドレイン）電流が供給さ
れ、上記第２のトランジスタのエミッタ（ソース）より
低インピーダンス出力が取り出される半導体回路。A first transistor to which an input signal is supplied and a collector (drain) connected to a power supply terminal and an emitter (source)
is grounded through a load impedance, and the output is taken out from the emitter (source).
a second □ transistor in a follower configuration and the first transistor in the follower configuration;
a coil connected in direct current between the collector (drain) of the transistor and the base (gate) of the second transistor, and the collector (drain) and base (gate) of the second transistor. It consists of a bias resistor connected in a DC manner, and a bias current (voltage) is supplied from the power supply terminal to the base (gate) of the second transistor via the bias resistor, and the bias resistor and the coil A semiconductor circuit in which a collector (drain) current is supplied to the first transistor through a series circuit, and a low impedance output is taken out from the emitter (source) of the second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3460381U JPS588206U (en) | 1981-03-12 | 1981-03-12 | semiconductor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3460381U JPS588206U (en) | 1981-03-12 | 1981-03-12 | semiconductor circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS588206U true JPS588206U (en) | 1983-01-19 |
Family
ID=29831925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3460381U Pending JPS588206U (en) | 1981-03-12 | 1981-03-12 | semiconductor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS588206U (en) |
-
1981
- 1981-03-12 JP JP3460381U patent/JPS588206U/en active Pending
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