JPS588362A - Test signal generating method for peripheral equipment - Google Patents

Abstract

PURPOSE:To easily perform the test for a ticket machine, etc. in a station without connecting an actual machine, by generating a test signal for a low speed peripheral equipment through the use of a microprocessor chip on the market and a small capacity of a memory. CONSTITUTION:A microcomputer device consists of a CPU1 consisting of a microprocessor IC, an RAM2 and a console 3. A program is executed, an address register is set to the head address of a data area, the address register is incremented, and an initial logical data ''0'' is read out. When data, e.g., 08 is read out at the data of the next address, the number of interruptions is counted and when the number of interruptions reach 8 times, the output logic is inverted from ''0'' to ''1''. When the end code FF is read out, the address counter is returned to the initial address and the test signal of the same pattern is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of generating a test signal that simulates a low-speed output signal such as that of a card reader.

Conventionally, when manufacturing controllers and interfaces for this type of peripheral equipment, it was necessary to actually connect the peripheral equipment and test and adjust it, which was particularly inconvenient when the computer and peripheral equipment were supplied by different manufacturers. There were many things like that. Furthermore, since a normal CPU is faster than a card reader, it is extremely difficult to create test data that simulates the output of a card reader. The present invention aims to solve the above problems and is comparative.

The present invention will be explained in detail below using examples. Figure 1a shows a schematic configuration of the device used in the present invention), in which a CPU (CPU) consisting of a microprocessor E.
) has an interrupt function (1), RAM memory (2)
and console (3) constitute a microcomputer unit. (4) is a clock generation circuit consisting of an oscillation circuit and a frequency dividing circuit; (5) is a timer interrupt circuit that generates an interrupt signal at intervals set by counting clock pulses; and (6) is an output means. As work 10
It is a port. The figure shows a memory map of the test' data storage section in memory (2), where the timer setting value, that is, the interrupt interval, is stored at the first address, and then the initial logic value of the test signal, that is, the test signal. Data indicating whether it starts with 1" or "+", then data expressing the duration of the same logic value, that is, the logic inversion interval, in terms of the number of interrupts within that period, are stored in sequence, and finally, the end of the test signal is stored. An end code indicating the process or a code instructing repetition is stored.

Figures 2 and 3 show specific examples;
The figure shows a specific example of the data in the memory area shown in FIG. 1 and is marked in hexadecimal. In the test data in this figure, "OF" at the first address (address 1000) indicates that an interrupt signal is generated by counting 15 clock pulses, and "00" at address 1001 indicates that the initial logic is "0".
It is assumed that "FF" indicates the initial logic "1". Addresses 1002 to 1009 represent the logical inversion interval in terms of the number of interrupts, and the waveform of the test signal formed by this data is shown in Figure 2a.
The days and winters below address 02 are respectively the section tl in Figure 2 a,
It corresponds to t2,5+・t8. 10.04 “
FFJ is the end code, and this end code is l-, FEJ
In this case, the same pattern shall be repeated. These data are stored in the console (3) before executing the program.
).

As shown in the flowchart in Figure 3, when the program is executed, the address register (A:om) is first set to the first address of the data area, that is, address 1000 on the upper side in the initial processing of (a), and in (b) A.D.
Read out the contents of address H, ie, the timer setting value "OF". Next, in (c), a timer is set and interrupt permission is granted. Next, in (d), the address registers (A, DR) are incremented, in (e), the contents of the ADH address, that is, the i-period logical data "00" are read out, and in (f), the initial logical value is set to 10'' in this example. Output.Initially (wa), -end of -
C, repeat, and -C are not detected, and these judgments are NO. Read the data ``08'' at the next address 1002 with Terasu Busy (G) and (C), and check the number of interrupts with <S). is counted, and when the number of interrupts reaches 8, the output logic is set to 0' with (nu).
"?" to "1" and then back to - again. Next logic inversion interval data "04".
” is read out, the interrupt signal is counted four times, and the skewer force is reversed. In the same way, the logical inversion is repeated in sequence, and when the end code ``FFJ'' is read, the program is terminated, and when the repeat code ``FE1'' is read, the address counter (ADH) is returned to address 1000 again and the same pattern is tested. In the example shown in Fig. 2, small numerical examples such as 8, 4, etc. are shown as logical inversion interval data, but in reality, numbers up to 256 are possible.
If you want to increase the reversal interval, set each data to 2.
It can be used as byte data. If the inversion interval is desired to be small, the interrupt interval set at the start address of the memory 2 may be set small.

Note that if the interrupt interval is also settable as in this embodiment, one byte of each data is sufficient. If you want to output an analog signal, use D/D as shown in Figure 1a.
This is possible by connecting an A converter (7).

As described above, according to the present invention, a low-speed test signal with a long inversion interval can be easily generated using a small number of bytes of data, and a low-speed test signal can be easily generated using a commercially available microprocessor chip and a large capacity memory. Since it is possible to generate test signals for peripheral devices, it has the advantage that it is easy to test and adjust interfaces, etc., or test station ticket gates, etc., without having to connect actual devices as in the past.

[Brief explanation of the drawing]

FIG. 1a is a block diagram showing an embodiment of the apparatus used in the method of the present invention, and FIG. 3 is a main part memory configuration diagram showing an example of the data as described above, and FIG. 3 is a flowchart of the same as above. (1) CPU, (2+ memory, (3) console, (4) clock generation circuit, (5) interrupt generation means (
Timer interrupt circuit, (6) is output means (■10 ports). Agent Patent Attorney Hiroshi Agata-Shin ←Basic black/ν Rini l, 5~

Claims (2)

[Claims] (1) Equipped with a CPU having an interrupt function, a memory, a means for generating interrupts at regular intervals, and an output means, and a plurality of data representing the initial logic and logic reversal interval of the test signal and a termination code are stored in the memory in advance. The reason why the initial logic is read out and the output logic is set is that each time the above data is read, the number of interrupts corresponding to each data value is counted and the output logic is set. A method for generating a test signal for a peripheral device, characterized in that the signal is inverted. (2) A test signal for a peripheral device according to claim 1, characterized in that the storage contents of the memory include data specifying an interrupt interval, so that the interrupt interval can be set in advance. How it occurs.