JPS5884307A - Programmable sequence controller - Google Patents

Abstract

PURPOSE:To ensure an optional control of a programmable sequence controller (PC) regardless of the states of other PCs, by having a wired OR connection between a control circuit of the PC and a synchronizing line and a data line respectively. CONSTITUTION:The control circuits CONT-C of PC1, PC2 and PC3 are connected with wired OR to a synchronizing line SYNC-LINE and a data line DATA LINE respectively via an output buffer OB which is capable of a wired OR connection and an input gate IG which regards a high impedance input as a high level input. In such way, a mutual link connection is secured among optional PCs so that the external definition data and reference contact data can be referred to as the common data. Thus, it is possible to separately drive or stop each PC and to perform an ON/OFF operation of a power supply.

Description

[Detailed Description of the Invention] This invention provides sequence control for various automated JII devices.
'agra! Regarding the programmable sequence controller (hereinafter referred to as PC) used for pulling, especially multiple OP
The PCs are interconnected to function as a single PO, and each PC has a function that can be controlled independently.

Traditionally, in large-scale manufacturing assembly lines, a single
Since controlling the entire system with c is 1-separation, a PC is provided for each station consisting of one individual control target, and these PCs are linked appropriately with O'f-R to control the entire twin. A controlling PC system is employed.

However, in the aforementioned nine PC system.

Each PC1- can be run or stopped independently.
There is no OFFFF control vehicle, so in order to create a system that can run and stop each PC independently and control the power supply ON/OFF, the Either a circuit must be created, or a link-coupled PCO must have the function of controlling other PCs, or a method such as using a higher-level combinator must be taken.

Therefore, as mentioned above, in a system where each PC can run and stop independently and cannot control the power supply, if one of the linked PCs breaks down, all other PO2 There is one point in the trench where the entire system is forced to stop and malfunction, and nine PCs are being repaired.

The ninth way to avoid this situation is to use the above-mentioned method to run and stop each PC independently.
A system capable of ON-OFF control would not only increase manufacturing costs, but also require 25 sequence programs! There is a drawback that only a small number of 70 contacts can be used effectively, and the 9th part cannot be used for link connection.

Therefore, the inventors of the present invention have conducted various studies in order to overcome all of the problems of the conventional PC system mentioned above, and finally, the PCO
The control circuit is wired or connected to the synchronization line and the data twin, respectively, and the external definition data and reference contact data of other PCs are configured to be linked so that they can be referenced as common data, so that they can be linked together. It has been found that in a PC system, each PC 1 can be operated or stopped individually, and the power supply can be turned on and off without stopping the system, thereby solving the problem mentioned above.

Therefore, an object of the present invention is to connect a plurality of pC9elJ links independently and connect them to other PCs without providing a special device for rounding the link connections, such as a dead PC controlling each pctH or a host combinator. A rounded program that constitutes a multiplex PC system that can arbitrarily perform stop operation and power ON-OFit' operation depending on the state of the PC (2 map sequence scene) provided by a-jl There is something to do.

In this issue 11, we aim to achieve the above objectives.

A programmable sequence controller or b*n that has the function of referencing reference contact data and externally defined "data I" of other programmable sequence controllers as common data. It is characterized by comprising means for wired-OR connection to each data line.

In the above-mentioned 10-gram pull sequence controller, the means for wired-OR connection is as follows.

It is preferable to consist of an output x7a that can be wired OR*a, and an input boot that is considered to be the same as a high impedance human input tX level input.

In the above case, the WIA that stopped with the electric sign in the ON state
, 5111 is configured to output a level output to the synchronous line, y, and data line. Also.

is configured to maintain an impedance state for the synchronization line and data line when the source is in the OFF state.

Next, an embodiment of the programmable sequence controller PC according to the present invention will be described in detail below with reference to the attached drawings.

FIG. 1 is a block circuit diagram showing the main configuration of a PC according to the present invention. That is, in FIG. 1, three PCs (PC/, PCJ, PCJ) are connected to each other and shown in good condition, and PCi, PCJ.

PCj is wired-OR connected to the synchronous twin 8YN (!-LINE and data line DATA LINK, respectively. In this case.

Each control circuit C0NT-C of PC/ , PCJ, and PCJ has an output
and further impedance to high level input and input (Goo) which is considered as PIo) through IQ.

Sync line 8YNC-(, I%m and data line D
Wired or connected to ATA LINE.

9. P related to the original 1jliK arranged in this way
CFi, %PC has a function that allows all linked PCs to refer to external definition data jl (internal definition data of other Opcs and main island contact data (internal definition data of each PC)) as common data. Therefore, if we show the state in which the external definition data and reference contact data are used in each sequence program in the nine PC/, PC, and PCJ linked and connected as shown in Figure 7, Figure 1 (
This is part 9 of a) to (6). Figure 2 (-) is.

PC/'s sequence program 2m is expressed as a relay ladder circuit, and 2nd m1(b) is a sequence program of PCJ expressed as a relay ladder circuit.
And 1 Octopus (O) Tsumugi, PCJ sequence program 2
The system is shown as a relay 2 circuit. In addition, No. J
In FiA (a) to (6), for the addresses assigned corresponding to each symbol, the pioneer code X represents input line point data, Y represents output contact data, and B represents the type of externally defined data, while the leading number 0 11 represents PCJ data, l represents PCJ data, and 1 represents PCJ data.

Therefore, referring to FIGS. 1(a) to (-), PCi.

PCJ and PCj are linked to each other m
I can make a calendar.

Next, the nine PCs shown in the first factor are mutually linked,
The operation of PCJ, PCJ, synchronization line 8YNC-1# LINK, and data line DATA LINE will be explained with reference to FIG. First, PC/, PCJ for synchronization line 8YNC-LINE
, PCj's output reaches a high level 1. (No. J
WA (J) I (j) $←)), synchronization 2 y8
YNC-LINlij high L/he/shi/tona 9 [see FIG. 3 (1)], PC/, PCJ, and PCJ are in a linked state. Therefore, from this link state, PC/.

PCJ, PCJ is data twin DATA LINh;
Output data to (jllJll(J I(4),
(7), (1)]. In this case, the data output configuration of each PC is determined by me, and each PC #i uses an internal clock to obtain its own output counter and outputs data to the data line. Therefore, the first quiz,
#i, PCi is a talker in ~ number, L PCJ
, PCJ is the zero-order tuning h~, which is the listener, and PC- is the toe force j), PC/, PCi
# Become an i listener.

And the last Thai torture is ~Naru & Teha.

PCJ)-force and &p, PC/, PCJ71-J,
List T-tonai.

Based on the operating characteristics described above, the PC according to the present invention 911 has the following characteristics:
In the 0N-OFF state of the power supply, the synchronization line 8YNC
- If the control circuit is configured so that LINK and DATA LINIC satisfy the true values shown in the hKi table, rolling and stopping during ON/OFF operation of the power of each linked PC can be performed independently. We meet through what we do.

Is l table H/Ls high (if) level and low (L) drop shape 1
There is 17fi.

Nene H111 Rubel's condition Nakamoto *HtZ! In a state of high impedance, then, based on the true value determination zero conditions shown in the above summary/table, the rules PCt, PCJ, P(
! J tc) 龜、PCJd! In case of suspension and PCJ
Synchronize with link-coupled PCt and PCJ when the power of
The operation with 15iy DATALINE will be explained with reference to Figure JII1.

First, when the PCJ power is OFF, synchronization line B
YNC-LINIA and data twin DATA L
The output for INE is island impedance (Hi
Z) Tona 9 [Compilation-(J) #(f)), PC/
and PCJd9 links to each data line D.
Normal output status for ATA LINIK [Edit #
Figure (4)]. Similarly, when the PC- is stopped and running with the power on, the outputs to the synchronization line 8YNC-LINK and the data line DATA LINK are at high level (H).9 [Compiled figure (4'), (P)] ),
PC/° and PCJ are linked and put into a normal output state for the data twin DATA LINE. In addition, in the case of Jin.

Tie-dengu t, ~t where PCJ should be the talker.

The fact that the output of PCJ is at a high level in Figure 1 means that the input gate (IG) is an inverted input in Figure 1, and the output data of PCJ is 10''. Therefore,
Using this fact, you can create other P in the sequence program.
The state of C can be known.

As is clear from the above, according to the present invention,
Connect the Pct wired OR to the P1 stage twin and data fin, and the PC stops when the power is on, and the output is at a high level for each 2 inputs in the brain.9. When the power source is OFF, the function is to increase the impedance to the social 2 input, and to link any 0PCt to each other to refer to external definition data and reference contact data as common data. By having j + % each PC can be independently retracted (linked) or stopped, and the power supply is 0N-
OFF operation becomes possible. Previously, other PCCs (PCCs) linked to each other are detected, and some 0I8I,
It is also possible to create a sequence pregtum that is at-. Therefore.

A large-scale PC according to the present invention! When a multiplex PC system is configured, even if one of the PCs fails, a situation in which the entire system must be stopped can be easily avoided.

Although the preferred embodiment 1 of the present invention has been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

Figure #l1 is a block diagram showing the connection arrangement configuration of the 10-guts maple sequence controller according to the present invention, and Figure 2 (&
) ~ (・) are mutually linked and combined nine progera! Pull sequence controller circuit diagram for each sequence controller, Figure 3 (1) to (f) are operational waveform diagrams of nine programmable sequence controllers linked together as shown in Figure 7. , g Figures (1) to (10) #i are operation waveform diagrams in an accident state of the mutually linked nine-wheel drive controller shown in the first WA. 8 YNC-L I Ng...Synchronization line DATA
LINK...Data line PC/, PC, PCJ.
... Programmable sequence; Control circuit OB... Output buffer IG... Input gate FIG, 1

Claims (4)

[Claims] (1) Reference contact data and other O/P graphics! Pull sequence control P-2 map pull sequence that has its own function by referring to externally defined data as common data; controller 2 or Rana 9, this programmable sequence controller and a program pull sequence controller having wired or subsequent means for each of the data lines. (2) In the programmable sequence controller described in claim 1 Ie, the wired-OR connection means includes an output buffer capable of wired-OR connection, and a high-impedance input connected to a high-level input and Oka et al. Programmable sequence controller 2 consisting of input gates and input gates. (3) In the programmable sequence controller 2 described in section 11j11/JJ circle line of % permission request, the power is turned on and the programmable sequence controller 2 is stopped and outputs a high level output to the WIA synchronization line and data twin. Programmable sequence control q-2゜ (4) In the programmable sequence controller 2 described in the @am/paragraph of the patent claim, the power is turned OFF.
A program pull sequence controller configured to maintain a high impedance state with respect to an F-shaped II synchronization line and data line.