JPS589092U - Pulse width modulation inverter - Google Patents
Pulse width modulation inverterInfo
- Publication number
- JPS589092U JPS589092U JP10216781U JP10216781U JPS589092U JP S589092 U JPS589092 U JP S589092U JP 10216781 U JP10216781 U JP 10216781U JP 10216781 U JP10216781 U JP 10216781U JP S589092 U JPS589092 U JP S589092U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- sample value
- value data
- wave sample
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Ac Motors In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す回路図、第２図及び第
３図は第１図の動作を説明するための波形図である。
５・・・インバータ、６・・・負荷、７・・・ゲートド
ライバ、１１・・・周波数設定器、１２・・・クッショ
ン回路、１３・・・電圧補正アンプ、１４・・・電圧−
周波数変換器、１５． １６． １７・・・カウンタ、
１８．１９・・・リードオンリーメモリ、２０・・・ア
ナログスイッチ、２２・・・デコーダ、２９・・・コン
パレータ、３１・・・出力制御回路、３′２・・・正逆
転制御回路。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams for explaining the operation of FIG. 1. 5... Inverter, 6... Load, 7... Gate driver, 11... Frequency setter, 12... Cushion circuit, 13... Voltage correction amplifier, 14... Voltage -
Frequency converter, 15. 16. 17...Counter,
18.19... Read only memory, 20... Analog switch, 22... Decoder, 29... Comparator, 31... Output control circuit, 3'2... Forward/reverse control circuit.
Claims (1)
数入力とするカウンタと、このカウンタの計数値をアド
レス徊号として正弦波サンプル値データと各相極性も含
めた相順データを順次出力する第１のメモリと、上記カ
ウンタの計数値をアドレス信号とするのに第１のメモリ
のアドレスよりも高い周波数になる該カウンタの計数値
とし搬送波サンプル値データと同期信号を出力する第２
のメモリと、この第２のメモリからの同期信号と周波数
設定電圧を条件として上記第１のメモリの最上位桁アド
レスを変えることで該メモリからの正弦波サンプル値デ
ータ出力の相順を切換える正逆転制御回路とを備え、上
記正弦波サンプル値データと搬送波サンプル値データと
からパルス幅変調パルス信号を得ることを特徴とするパ
ルス幅変調方式インバータ。A counter whose counting input is a frequency signal proportional to the inverter output frequency setting value, and a first circuit which sequentially outputs sine wave sample value data and phase sequence data including each phase polarity using the count value of this counter as an address reference signal. a memory, and a second memory for outputting carrier wave sample value data and a synchronization signal by using the count value of the counter as an address signal and having a frequency higher than the address of the first memory.
memory, and a method for switching the phase order of the sine wave sample value data output from the second memory by changing the most significant digit address of the first memory, subject to the synchronization signal and frequency setting voltage from the second memory. A pulse width modulation type inverter, comprising: a reversing control circuit, and obtaining a pulse width modulated pulse signal from the sine wave sample value data and the carrier wave sample value data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10216781U JPS589092U (en) | 1981-07-09 | 1981-07-09 | Pulse width modulation inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10216781U JPS589092U (en) | 1981-07-09 | 1981-07-09 | Pulse width modulation inverter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS589092U true JPS589092U (en) | 1983-01-20 |
Family
ID=29896819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10216781U Pending JPS589092U (en) | 1981-07-09 | 1981-07-09 | Pulse width modulation inverter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS589092U (en) |
-
1981
- 1981-07-09 JP JP10216781U patent/JPS589092U/en active Pending
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