JPS5892736U - Carrier body for integrated circuits - Google Patents

Carrier body for integrated circuits

Info

Publication number
JPS5892736U
JPS5892736U JP18828281U JP18828281U JPS5892736U JP S5892736 U JPS5892736 U JP S5892736U JP 18828281 U JP18828281 U JP 18828281U JP 18828281 U JP18828281 U JP 18828281U JP S5892736 U JPS5892736 U JP S5892736U
Authority
JP
Japan
Prior art keywords
bottom wall
wall
right sides
side walls
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18828281U
Other languages
Japanese (ja)
Other versions
JPS6140695Y2 (en
Inventor
小路 勝博
康豊 小宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP18828281U priority Critical patent/JPS5892736U/en
Publication of JPS5892736U publication Critical patent/JPS5892736U/en
Application granted granted Critical
Publication of JPS6140695Y2 publication Critical patent/JPS6140695Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るキャリア本体の層構成の説明図で
ある。第2図はキャリア本体の部分切欠展開図である。 第3図はキャリア本体の一部組立斜視図である。第4図
は組立を完了したキャリア本体にLSIを跨架したもの
を筒体と共に示す部分切欠斜視図、第5図は第4図示の
ものを組合わせた状態における垂直断面図である。 10・・・・・・紙層、12・・・・・・金属箔層、1
6・・・・・・底壁、18. 20. 22. 24・
・・・・・側壁、28・・・・・・起立片、30・・・
・・・打抜線、34・・・・・・切込、3B・・・・・
・LSI、40・・・・・・LSIの端子。
FIG. 1 is an explanatory diagram of the layer structure of the carrier body according to the present invention. FIG. 2 is a partially cutaway developed view of the carrier body. FIG. 3 is a partially assembled perspective view of the carrier body. FIG. 4 is a partially cutaway perspective view showing the fully assembled carrier main body with the LSI mounted thereon, together with the cylindrical body, and FIG. 5 is a vertical cross-sectional view of the combined state of the carrier body shown in FIG. 10...Paper layer, 12...Metal foil layer, 1
6...Bottom wall, 18. 20. 22. 24・
... Side wall, 28 ... Standing piece, 30 ...
...Punching line, 34...Depth of cut, 3B...
・LSI, 40... LSI terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 帯状シートのその長手方向に沿う中心部に底壁を区画形
成し、その左右に第一側壁を区画形成し、さらにその左
右に第二側壁を区画形成し、少なくとも第一・第二側壁
境界部に金属層を積層し、かつ、上記底壁の左端から始
まり左第−側壁、底壁、右第−側壁を経て底壁の右端で
終わる打抜線、当該打抜線で囲まれた部分を横断する折
線及び当該折線との対向端における切込により起立片を
複数個構成し、上記第一、第二両側壁を重合せしめると
共に底壁の左右から起立せしめ、上記起立片の切込を上
記側壁の上記打抜線縁部に食い込ませてなる集積回路用
キャリアの本体。
A bottom wall is defined at the center along the longitudinal direction of the strip sheet, first side walls are defined on the left and right sides of the bottom wall, second side walls are defined on the left and right sides of the bottom wall, and at least the first and second side wall boundaries are defined. A metal layer is laminated on the bottom wall, and a punching line starts from the left end of the bottom wall, passes through the left side wall, the bottom wall, the right side wall, and ends at the right end of the bottom wall, and the area surrounded by the punching line is A plurality of upright pieces are formed by a transverse fold line and a cut at an end opposite to the fold line, and the first and second side walls are overlapped, and are made to stand up from the left and right sides of the bottom wall, and the cut of the above-mentioned rise piece The main body of the integrated circuit carrier is formed by biting into the edge of the punched line on the side wall.
JP18828281U 1981-12-17 1981-12-17 Carrier body for integrated circuits Granted JPS5892736U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18828281U JPS5892736U (en) 1981-12-17 1981-12-17 Carrier body for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18828281U JPS5892736U (en) 1981-12-17 1981-12-17 Carrier body for integrated circuits

Publications (2)

Publication Number Publication Date
JPS5892736U true JPS5892736U (en) 1983-06-23
JPS6140695Y2 JPS6140695Y2 (en) 1986-11-20

Family

ID=29991718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18828281U Granted JPS5892736U (en) 1981-12-17 1981-12-17 Carrier body for integrated circuits

Country Status (1)

Country Link
JP (1) JPS5892736U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895698U (en) * 1981-12-23 1983-06-29 大日本印刷株式会社 Carrier body for integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895698U (en) * 1981-12-23 1983-06-29 大日本印刷株式会社 Carrier body for integrated circuits

Also Published As

Publication number Publication date
JPS6140695Y2 (en) 1986-11-20

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