JPS589561B2 - barista - Google Patents

Description

[Detailed description of the invention] This invention relates to polycrystalline varistors.

More particularly, this invention relates to a novel electrode arrangement of polycrystalline varistors for improving the uniformity of current flow through a series stack of polycrystalline varistor elements for high voltage surge protection.

Several materials are known whose resistance characteristics are nonlinear and are represented by the equation (1)(y)Ct.

where ■ is the current flowing through this material, ■ is the voltage applied to this material, C is a constant determined by the physical dimensions of the object, its composition, and the parameters of the manufacturing process of this object, and α is It is a constant for a certain range of current, and represents the degree of nonlinearity of the resistance characteristics of this object.

One well-known example of such a varistor material is silicon carbide.

Silicon carbide and other non-metallic varistor materials are characterized by an alpha index of 6 or less.

A family of polycrystalline metal oxide varistor materials exhibiting alpha indices greater than 10 have recently been produced.

These new varistor materials include sintered bodies of zinc oxide grains, as well as grains of other metal oxides and/or halides, such as beryllium oxide, bismuth oxide, bismuth fluoride, or cobalt fluoride. and an interlayer, which is described in U.S. Pat. No. 3,682,841} and U.S. Pat. No. 3,687,871.

In power distribution technology, high-voltage surge protectors are installed at various points in the power distribution network to protect the elements of the power distribution circuit and the equipment of the power consumer from damage caused by high-energy surges caused, for example, by lightning strikes or transient load abnormalities. It is normal to protect

Spark gaps and silicon carbide varistors have been used in the past for this purpose.

Silicon carbide, used for surge protection, has a relatively low value of alpha index, so new metal oxide varistor devices, which are usually connected in series with the spark gap, have better performance as varistors. Therefore, it is theoretically possible to provide superior performance in transient voltage suppression stacks for power distribution systems.

As polycrystalline metal oxide varistors are currently manufactured, the varistor materials described above are pressed into a disk-shaped body having a pair of opposing major surfaces, and then sintered. Creates a semilac ballista disc.

A pair of electrodes is applied to opposing major surfaces of each disk.

High voltage stacks for protection in power distribution systems are made by stacking a suitable number of electroded disks in series.

Silicon carbide varistor stacks for high voltage surge protection are formed in a similar manner.

However, in the case of polycrystalline metal oxide varistors, extremely high values of alpha index give excellent varisque performance;
One problem arises in high voltage, high energy stacks.

It is because the negative effects of non-uniformity of the varistor characteristics within the disk are magnified, leading to undesirable current channeling (
channeling) occurs.

In polycrystalline metal oxide varisque disks, small changes in varistor voltage cause very large changes in the current distribution through the disk.

When this channeling of current occurs within the disk, almost all of the current flowing across the disk between the electrodes is carried by the very small cross-sectional area of the disk, creating thermal stresses within the disk and causing the disk to or cause premature disk failure.

In the case of a high voltage surge suppression stack consisting of multiple disks with a unitary electrode on each major surface of each disk, current channeling occurs through the weakest portion of each disk resulting in the adverse effects described above.

It is therefore an object of this invention to provide a polycrystalline metal oxide varistor element that is packaged within a high energy distribution surge suppression stack to prevent selective channeling of current through the elements of the stack and The purpose is to increase the reliability of the body.

Another object of the present invention is to provide a polycrystalline varistor element having patterned discontinuous electrodes on opposing major surfaces, the interface between successive disks of the stack? By preventing equipotential surfaces from forming, selective current channeling through the disk is prevented.

Another object of this invention is to provide a high energy, high voltage surge suppression stack with improved uniformity of current distribution within the stack.

Briefly, in accordance with an embodiment of the invention, a body of polycrystalline varistor material having a pair of opposing planar surfaces or a number of discontinuous electrodes applied to each of the opposing planar surfaces.

These electrodes provide electrical contact to the body of polycrystalline varistor material, but their discontinuity prevents the existence of equipotential surfaces at the surface of the varistor body.

In another embodiment of the invention, a plurality of varistor bodies having discontinuous, patterned electrodes on the major surface of each varistor body are stacked in series to form a high energy, high voltage surge suppression stack. in which case a substantially uniform current distribution occurs within the stack i when the voltage across the stack exceeds the varistor voltage.

This uniform current distribution results from the absence of equipotential surfaces between the elements of the stack, and uniform current distribution throughout the stack improves reliability and performance.

FIG. 1 shows electrodes 11 and 12 on opposing main surfaces, respectively.
Varistor element 1 having 21 and 22, 31 and 32
2 illustrates prior art polycrystalline Barytas stacks including 0, 20 and 30.

Due to the non-uniformity of the material of the varistor elements 10, 20 and 30, each element has preferential current paths 13, 23 and 33 therein, respectively.

The electrodes 12 and 21 and the electrodes 22 and 31 are the varistor element 1
By providing equipotential surfaces at the 0 and 20 and 20 and 30 junctions, there is a preferential current path throughout the stack.

As a result, when a voltage surge occurs that exceeds the varistor voltage of the stack, nearly all of the current flowing through the stack is transferred to the preferential current paths 13, 2 of the stack components.
3 and 33.

As a result, the vicinity of the current path may be locally heated and one or more of the elements in the stack may be shattered and the stack may be destroyed, or the varistor elements or the electrodes applied thereto may be electrochemically can be damaged and reduce the performance of the stack.

In accordance with the present invention, channeling of current within a high energy, high voltage surge suppression stack is prevented by applying patterned electrodes to the elements of the stack, as illustrated in FIG.

FIG. 2 shows one major surface of a polycrystalline varistor element 40 included in a high energy, high voltage surge suppression stack with electrode means applied to the major surface.

The electrode means applied to the surface of the varistor disk 40 according to the invention includes electrically conductive elements 41 applied to the surface of the disk 40 in a discontinuous pattern.

Due to the discontinuity of the electrode means according to the invention, there are no equipotential surfaces at the interfaces between the elements of the stack, which prevents the channeling of current through the entire stack and prevents such channeling. Harmful effects are prevented.

Since the preferential current paths are randomly located within the individual polycrystalline varistor elements, the patterned arrangement of the electrodes in accordance with the present invention allows the current to follow the preferential paths in each disk of the stack. By preventing flow, the effective uniformity of the entire stack is greatly improved.

Conductive element 4 of the patterned electrode shown in FIG.
1 is illustrated as a square, but the present invention is not limited to this, and other patterns may be used.

The geometry of the pattern is also a matter of design choice, but spacing the conductive elements 41 too large may undesirably reduce the effective volume of the available varistor elements 40, and the spacing may be too small. It should not be overdone to create undesirable conductive paths between adjacent electrode elements 41 on the surface of the varistor element 40.

Optimally in practicing the invention, the conductive elements 41 of the patterned electrode should occupy approximately two-thirds of the surface area of the varistor element 40, with the non-conductive regions 45
should occupy approximately one-third of the surface area of the varistor element 40.

Each of the conductive elements 41 covers 3 of the surface area of the varistor element 40.
% or less.

FIG. 3 is a cross-sectional view of a portion of a high energy, high voltage surge suppression stack according to the present invention including a plurality of varistor elements shown in FIG. 2;

FIG. 3 shows varistor elements 40, 50 and 60 having patterned electrodes on opposing major surfaces.

The varistor element 40 includes a conductive element 41 shown in FIG. 2 on its first surface, and a conductive element 42 on its opposite surface.

Similarly, varistor elements 50 and 60 each have conductive elements 51 and 52 and 61 and 62 on their opposite sides.

When a voltage surge exceeding the varistor voltage of the stack illustrated in FIG. 3 occurs, the varistor elements 40, 50 of the stack
A conductive path through and 60 exists between opposing pairs of electrodes on opposite sides of each disk.

Because the electrodes are arranged in a pattern, there are no conductive paths along the interfaces of adjacent varistor elements.

Accordingly, the current flowing through the varistor stack of FIG. 3 is prevented from selectively channeling through the discs of the stack, as described above with respect to FIG.

Therefore, the varistor elements 40 and 50 constituting the stacked body
and 60, the current distribution within the stack of FIG. 3 is further made uniform.

FIG. 4 shows another embodiment of a varistor stack according to the invention, with the modification that the insulating material is provided on the electrode surface associated with each varistor element complementary to the pattern of the conductive elements. It is included in a similar pattern.

In FIG. 4, varistor element 70. 80 and 90 have patterned electrodes on their opposing surfaces, respectively;
A conductive element 71 surrounded by an insulating material 73 on the first main surface of the varistor element 70 , a conductive element 72 surrounded by a gimlet material 74 on the second main surface of the varistor element 70 , and a varistor element 80 facing each other A conductive element 81 surrounded by an insulating material 83 on its main surface, a conductive element 82 surrounded by an insulating material 84, and a conductive element 82 surrounded by insulating materials 93 and 94 on the opposing main surfaces of the varistor element 90, respectively. sexual element 9
1 and 92.

Including insulating material on the electrode surface helps to increase the electrical breakdown strength between adjacent conductive elements of the patterned electrode and also helps protect the varistor stack from ambient contamination.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a portion of a high energy, high voltage surge suppression stack illustrating the deleterious effects of channeling current through the stack. FIG. 2 is a plan view of one polycrystalline varistor element included in a high energy, high voltage surge suppression stack according to the present invention having patterned electrodes on its major surface. FIG. 3 is a cross-sectional view of a high energy, high voltage surge suppression stack according to the present invention. FIG. 4 is a cross-sectional view of a portion of a high-energy, high-voltage surge suppression stack according to the present invention, in which insulating material is applied to the major surfaces of the elements of the stack in a pattern complementary to the electrodes. It is strained. Explanation of main symbols, 10, 20, 30, 40, 50, 60
, 70, 80, 90: Balisk element, 11, 12, 2
1, 22, 31, 32: electrode, 4L42, 5L52, 6
1,62,71 ,72,81 ,82,91 ,92
: Conductive element (electrode), 73, 74, 83, 84, 93
, 94: Insulator.

Claims (1)

[Claims] 1. In such a polycrystalline varistor element included in a series stack of polycrystalline varistor elements for high voltage surge protection, a body of polycrystalline varistor material having a pair of opposing flat surfaces and a body of polycrystalline varistor material having a pair of opposing flat surfaces; electrode means applied to each of the flat surfaces to provide electrical contact to said body, said electrode means being arranged in a pattern such that there are no equipotential surfaces on said surfaces; A polycrystalline varistor element 2 in a high energy, high voltage surge suppression stack having a plurality of bodies of polycrystalline varistor material stacked in series, on each of a pair of opposing surfaces of each said body. The body has a plurality of conductive elements arranged in a predetermined geometric pattern, and the bodies are stacked in series, and each conductive element is connected to a corresponding conductive element arranged in an adjacent body. The high-voltage devices are arranged in such a way that they are in contact with each other, so that the bodies are electrically interconnected in series, and there is no equipotential surface along the joint between adjacent bodies. Energy high voltage surge suppression stack.