JPS591209U - digital amplitude modulation circuit - Google Patents
digital amplitude modulation circuitInfo
- Publication number
- JPS591209U JPS591209U JP9544582U JP9544582U JPS591209U JP S591209 U JPS591209 U JP S591209U JP 9544582 U JP9544582 U JP 9544582U JP 9544582 U JP9544582 U JP 9544582U JP S591209 U JPS591209 U JP S591209U
- Authority
- JP
- Japan
- Prior art keywords
- modulator
- modulation signal
- amplitude modulation
- modulation circuit
- coarse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplitude Modulation (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の適用される振幅変調された高周波信号
の波形図、第２図Ｃ−ｉ本考案の実施例を示すブロック
図、第３図は変調器のバイアス電流対減衰量の特性図、
第４図は第２図の粗相の記憶素子および密用の記憶素子
によるデータ書き込み例を示す特性図である。図におい
て
１．１・・・・・・スタート信号入力端子、１２・・・
・・・クロック信号入力端子、１３・・・・・・カウン
タ、１４・・・・・・粗相の記憶素子、１４′・・・・
・・密用の記憶素子、１５．１５’ ・・・・・−Ｄ／
Ａコンバータ、１６・・・・・・加算回路、１７・・・
・・・変調器、２０・・・・・・ＲＦ入力端子、２１・
・・・・・ＲＦ出力端子、である。Fig. 1 is a waveform diagram of an amplitude-modulated high-frequency signal to which the present invention is applied, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a characteristic of bias current versus attenuation of the modulator. figure,
FIG. 4 is a characteristic diagram showing an example of data writing by the coarse-phase storage element and the dense-phase storage element of FIG. In the figure, 1.1...start signal input terminal, 12...
...Clock signal input terminal, 13...Counter, 14...Coarse phase memory element, 14'...
...secret memory element, 15.15' ...-D/
A converter, 16...Addition circuit, 17...
...Modulator, 20...RF input terminal, 21.
...RF output terminal.
Claims (1)
の変調信号としての入力信号をデジタル的に入力する入
力手段と、この入力手段のデジタル値に対応して前記変
調器の出力に所定電圧ステップで所定波形を得るように
予め定めた値を記憶させた粗記憶手段と、前記入力手段
のデジタル値に対応して前記変調器の出力波形に対応し
て前記電圧ステップを補うように予め定めた値を記憶さ
せた密記憶手段と、これら粗および密記憶手段の各デジ
タル出力をアナログ電圧にそれぞれ変換するＤＡ変橡手
段と、これ９−ＤＡ変換手段の出力を所定比率で加算す
る加算手段と、この加算手段の出力を前記変調信号とし
て前記変調器に供給する手段とを含むデジタル振幅変調
回路。a modulator that modulates the amplitude of a high frequency signal using a modulation signal; an input means that digitally inputs an input signal as the modulation signal; coarse storage means storing a predetermined value so as to obtain a predetermined waveform; and a predetermined value corresponding to the digital value of the input means and corresponding to the output waveform of the modulator to compensate for the voltage step. 9-DA conversion means for converting the digital outputs of the coarse and fine storage means into analog voltages, and addition means for adding the outputs of the 9-DA conversion means at a predetermined ratio; and means for supplying the output of the adding means to the modulator as the modulation signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9544582U JPS591209U (en) | 1982-06-25 | 1982-06-25 | digital amplitude modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9544582U JPS591209U (en) | 1982-06-25 | 1982-06-25 | digital amplitude modulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS591209U true JPS591209U (en) | 1984-01-06 |
| JPS6329287Y2 JPS6329287Y2 (en) | 1988-08-08 |
Family
ID=30227926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9544582U Granted JPS591209U (en) | 1982-06-25 | 1982-06-25 | digital amplitude modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS591209U (en) |
-
1982
- 1982-06-25 JP JP9544582U patent/JPS591209U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6329287Y2 (en) | 1988-08-08 |
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