JPS5913073B2 - Fixed line method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line-setting method in a preprocessing section of a character reading device, particularly a handwritten character reading device.

A conventional preprocessing section is shown in FIG.

In FIG. 1, 1 is a binary digital signal from a photoelectric converter, gate 2 is a filter, and 3 is a pattern register.Since filter 2 was able to remove quantization noise, In the case of characters with very thick lines or very thin lines, it was often difficult to read the characters. Additionally, some devices are equipped with a thinning circuit, but if the line is made too thin, the character pattern may be deformed and misread, as shown in Figure 2. The purpose of the present invention is to eliminate these drawbacks by preventing thick portions from narrowing below a certain width, and by widening very thin portions, which will be described in detail below.

FIG. 3 is a block diagram of a fixed line method in a preprocessing section showing the first embodiment of the present invention, in which 4 is a binary input signal obtained by photoelectrically converting a character figure, and 95 is a thin line. circuit,
6 is the output signal of the thinning circuit, T is the test circuit, 8 is the thickening circuit control input signal, 9 is the thickening circuit pattern input signal,
10 is a thick line conversion circuit, and 11 is a constant line conversion output signal.

In FIG. 3, the line thinning circuit 5 performs line thinning under certain conditions, and uses the binarized input signal 4 as input to generate 3 x 3 bits and 5 x 5 bits centered on the bit of interest. Examine the peripheral path (hereinafter referred to as peripheral) and obtain the black and white information of specific bits (top, bottom, left and right of the bit of interest) in 3 x 3 bits, as well as the information from white to black or from black to white in 3 x 3 bit '0' and 5 x 5 bit. The value (white or black) of the bit of interest determined by the number of change points is output.

Next, the inspection circuit 7 detects control information for thickening the line under certain conditions, and from the output signal 6 of the thinning circuit 5, 3×3 bits centered around the bit of interest and 5×
The area around the 5 bits is examined in the same way as the thinning circuit 5, and the value of the bit of interest determined by the black and white information of the specific bit and the number of changing points is output as the thick line circuit control signal 8 and the output of the thinning circuit 5. The signal 6 is also outputted as it is as a bold circuit pattern input signal 9.

Next, the thickening circuit 10 thickens the line under certain conditions, and uses the output signal 8 from the inspection circuit 7 to determine the bit t of interest.
The surroundings of the 3X3 bits in the center are examined, and the position and the target bit are determined by the presence or absence of control information (control information that does not narrow down) around the center and the black and white information of the target bit of signal 9 synchronized with signal 8. Outputs the value (white or black).

The output 11 of this thick line forming circuit 10 is the final output of the line forming circuit 10. The output 11 of the thickening circuit 10 is input to a pattern register (not shown). In the present invention, a black bit means a logical value "1", and a white bit means a logical value "0".

FIG. 4 is a diagram showing details of the thinning circuit 5 in FIG. 3. Note that the inspection circuit 7 also has the same configuration. In Figure 4, 4-1, 4-2,...4-5
are binary pattern input signals, 13-1, 13-2
,...,13-5 is a shift register with 5 columns, consisting of the number of bits corresponding to the field of view of the valley sensor, and 2
This is for the case where the digitized pattern input signal is input serially. Also 14-1, 14-2, 14-5
is a shift register with 5 columns, each column has 5 bits, and the output of each bit is XOνX1×2t゜゜゜゜゛)X24. These shift registers 14-1, 14-2,...
..., 14-5 is the bit of interest X. The purpose is to investigate the surroundings of 3x3 bits and 5x5 bits centered on . Bits X1 to X8 are bits of interest. The periphery of 3×3 bits centered on the bit XO is shown, and bits X, to X24 are the periphery of 5×5 bits centered on the bit of interest XO. 15-1, 15-2, ..., 15-24 are exclusive ORs (Ex
exclusiveOR) circuit, each output is Y,,y2,y2
It is 4.

16-1 and 16-2 are arithmetic circuits, and the arithmetic circuit 16
-1 is the focus point X.

It calculates the number of transition points from white to black or from black to white along the periphery of 3 × 3 bits centered on (
Σ y )/゛2 (denominator 2 is black → white or white → n = 1n
This is to focus on one side of the black color.
The arithmetic circuit 16-2 calculates the number of transition points from white to black or from black to white along the periphery of 5×5 bits centered on the bit of interest XO, (Σ y )
/2 (the denominator 2 is the same as in the case of the n=9n arithmetic circuit 16-1) is output to Y3.

17 is a 4AND circuit that inputs specific bits X2, X4, X6, and X8.

is its output. The conditions for determining the value of the target bit in the thinning circuit 5 are as follows: (Condition 1) (Condition 2) XO = "0"5's output 6 is HOut = "O" XO = "1" , HOut=[O] only when YA=YB=1 and Yc=[0], and HOut=[1] otherwise, it is a thinning circuit.

In other words, the bit of interest is X.

The bit of interest is X as the output value. If is white and the bit of interest is X. The number of changing points YA and the bit of interest X along the periphery of 3×3 bits centered on . The number of change points YB along the periphery of 5×5 bits centered on is both 1 and the bit of interest is X. Logical product Y of specific bits X2'X49X6'X8 around 3x3 bits centered on . is "O" and the bit of interest is X. Set to "0" only if is black,
The others are set to "1". Furthermore, the conditions for determining the value of the bit of interest in the inspection circuit 7 having the same circuit configuration as the thinning circuit 5 are as follows:
When YA, YB, and Yc are defined by the above equations (1) to (3), (condition 3) when XO = "O", the output 8 of the test circuit 7 is KOut = [0] (condition 4) If XO=“1”, (YA>or YB>2) and Y.

Only if "0" KOut2[1], Otherwise, KOut="0" It is.

In other words, the bit of interest is X.

The bit of interest is X as the output value. The number of changing points YA along the periphery of the central 3X3 bit is 2 or more, or the bit of interest is X. The number of change points YB along the periphery of 5 × 5 bits centered on is 2 or more and the bit of interest
. Specific bits around the 3x3 bits centered around
1” and the others are 0. FIG. 5 is a diagram showing details of the thick line circuit 10 in FIG. 3. In FIG. 5, 8-1, 82, and 8-3 are output signals of the inspection circuit 7 and are signals for controlling the bold line circuit. 9-1 and 9-2 are output signals of the inspection circuit 7, which are thick line circuit pattern input signals.

19-1, 19-2, 19-3 are shift registers 13-
This is the same shift register as 1 to 13-5, but has three columns, and the thick line circuit control signal is input serially.

20-1, 202, and 20-3 are shift registers with three columns, each column consisting of three bits, and the output of the valley bit is C.

,C,,C2...,C8. Also 21-1,
The shift register 21-2 is the same as the shift registers 19-1 to 19-3, and has two columns, and is used when the bold circuit pattern input signal is serially input.The output of the second bit of the shift register 22 is P. It is. Bits C1 to C8 of shift registers 20-1 to 20-3 are bit C of interest. The bit PO of the shift register 22 shows the target bit of the thick line circuit pattern input signal (the same signal as the output signal of the thin line circuit 5) synchronized with the thick line circuit control signal. There is. 23 is an 80R circuit which receives bit outputs C1 to C8 as input;
is an 0R circuit whose inputs are the output of the 80R circuit 23 and the bit output PO.

The value of the bit of interest in such thick line conversion circuit 10 is defined by the following equation.

F0ut=PO(ΣC) ・・・・・・・・・(
4) m-1m, that is, the bit C of interest.

The bit C of interest is the output value of . There is one or more pieces of black information (control information that does not narrow down) around the 3X3 bit centered on , or the bit C of interest is there. Bit P synchronized with. If it is black information, set it to "1", otherwise set it to "O".
shall be. The above FOut is the final output of the constant line conversion.

FIGS. 6 and 7 show specific examples of the line straightening method according to this embodiment.

(In Figures 6 and 7, the x marks represent black bits.) Figure 6 shows the case where a thin line is made into a constant line, and Figure 6a shows the input to the thinning circuit 5. FIG. 6b is a pattern obtained by thinning the pattern of FIG. 6a according to (condition 1) and (condition 2) of the thinning circuit 5. FIG. 6c is a pattern that is the result of testing the pattern in FIG. 6b to see if it can be narrowed by (condition 3) and (condition 4) of the inspection circuit 7, and is a line edge pattern that cannot be narrowed any further. It shows. Figure 6 d is Figure 6 c
This is a pattern obtained by making the pattern into a thick line according to the condition defined by equation (4) of the thick line making circuit 10, and reduces the constant line state. 7 shows a case where a thick line is made into a constant line, FIG. 7a is a binary pattern input to the thinning circuit 5, and FIG. 7b is an output of the thinning circuit 5. It's a pattern.

Figure 7c shows the output pattern of the test circuit 7, and the black bits are not bright, which indicates that the pattern in Figure 7b cannot be made any thicker, and the pattern shown in Figure 7d is thickened. The output pattern of circuit 10 will be the same as that in FIG. 7b. As explained above, in the first embodiment, thick lines are first thinned by passing them through a thinning circuit.

However, since thin lines are inspected in the 3×3 and 5×5 ranges, consideration is given to ensuring that continuous thin lines do not break. Next, very thin lines can be made thicker by passing them through the thickening circuit, so the combination of the thinning circuit and the thickening circuit has the advantage that a character pattern having a substantially constant line width χ can be obtained. General 11CO. If you sample a character written with Sharp Vencil using a 5ml lead at around 100μm, the line width will be about 8 to 2 samples, so first pass it through 2 to 3 stages of thinning circuit, then thicken it. 1
By passing through the layers, a pattern with a line width of about 4 to 2 samples is obtained. Further, if the number of stages of line thinning is increased too much, the distortion of the pattern becomes large, so from this point of view as well, this number of stages is desirable. Further, in the first embodiment, each circuit was explained using arithmetic elements, but by using a ROM, the packaging density can be increased and similar effects can be obtained.

Furthermore, a desirable pattern can be obtained in the output by placing a conventional simple noise removal filter before and after the linearization circuit. 1st
In the embodiment, Y in the case of (condition 2) in the thinning circuit.

Although the condition that =0 is included, the same effect can be obtained even if a thinning circuit excluding this condition is used as the second embodiment. That is, the conditions for determining the value of the target bit of the line thinning circuit of the second embodiment are (Condition 1) (Condition 5) When XO = "0", HOut = "O", When XO = "1" , HOut="0" only when YA=YB=1, otherwise HOut="1".

In other words, the bit of interest is X.

The bit of interest is X as the output value. If is white, and focus point X. The number of changing points YA and the bit of interest X along the periphery of 3×3 bits centered on . The number of changing points YB along the periphery of 5×5 bits centered on is both VCl and the bit of interest is X. Set to "0" only if is black, otherwise [
1". Moreover, in the thinning circuit of the first embodiment, 3X
Even if the bit of interest is at the edge of the line around the 3rd bit, if the specific bit (upper, lower, left, or right bit) is black, that bit will not be thinned (under the condition of YO'-0), so the diagonal line will be the 8th line. As shown in Figure a, the lines are thinned at a rate of 1/Jn compared to horizontal or vertical lines, and the amount of thinning varies depending on the shape of the pattern and may cause distortion.

In the thinning circuit of the second embodiment, on the other hand, diagonal lines are compared to horizontal or vertical lines as shown in FIG. 8b! It is narrowed down at a rate of 2.

Therefore, as a third embodiment, the thinning circuit A used in the first embodiment and the thinning circuit B used in the second embodiment are used as the thinning section, and the odd-numbered stages are thinned circuit A and the even-numbered stages are thinned circuit A. If the stages are made into thinning circuit B, or the odd-numbered stages are made into thinning circuit B and the even-numbered stages are made into thinning circuit A, the thinning ratio becomes equal, and a constant line pattern with even less distortion can be obtained. . 9 and 10 show specific examples of a fixed line method using three stages of line thinning circuits. This is the case of the third embodiment in which the thinning circuit B is used in several stages and the thinning circuit A is used in even stages.

Note that the x marks in FIGS. 9 and 10 indicate black bits of the original pattern, and the 2 marks indicate black bits of the regular output pattern. As is clear from FIGS. 9 and 10, in the third embodiment, a fixed line pattern with even less distortion can be obtained. In the line thinning methods according to the first and second embodiments, the sixth
As shown in Figures a and b, both ends of the line are significantly shaved off (by a length equivalent to 2 bits in a black bit pattern) in one stage of line thinning, resulting in a shortened line.

Therefore, the above-mentioned drawbacks can be eliminated by adopting a line thinning method using a line thinning circuit according to (condition 1) and (condition 6) described below as the fourth embodiment. (Condition 1) If XO = “0”, HOut = “o” (Condition 6) If XO = “1”, HOut = “O” only if YA:YB = 1 and Yc = YO2 “0” , Others are HOut2 "1-! However, if 24≧K, Y.

= [0”Σ Y if n=9n<K.

= “1” (K is a constant) In other words, the bit of interest is X.

The bit of interest is X as the output value. If is white 0 and the target bit X. The number of change points YA and the bit of interest X along the periphery of 3X3 bits centered on . The number of change points YB along the 5×5 bits around the center are both 1 and the bit of interest is X. Logical product Y of specific bits X2, X4, X6, and X8 around 3×3 bits centered on . is "O", and the number K of black information surrounding the 5x5 bits centered on the focused pit XO is a certain number or more, and the focused bit X. It is set as [0] only when is black, and set as [1] otherwise.
According to the fourth embodiment, even if the pattern shown in FIG. 6A is thinned, the same pattern remains and the ends of the line are not shaved, so even if a multi-stage thinning circuit is used, the line length will not be significantly shortened.

Generally, a value of 4 to 3 is appropriate for K, and in this embodiment, K=3. Further, as a fifth embodiment, the same effect as the fourth embodiment can be obtained even if a line thinning method using a line thinning circuit according to (condition 1) and (condition 7) described below is adopted. (Condition 1) In the case of XO-“O”, HOut=“O” (Condition 7) In the case of XO-“1”, YA=YB=1 and Y.

Only if = “0” HOut=[o”, Others are HOut2 [1] however Y if 24≧K.

-[0"n&Xn<-M then YD=[1" (M is a constant) In other words, the bit of interest is X.

The bit of interest is X as the output value. If is white and the bit of interest is X. The number of changing points YA and the bit of interest X along the periphery of 3×3 bits centered on . The number of change points YB along the periphery of 5×5 bits centered on is both 1 and the bit of interest is X. The number K of black information surrounding the 5×5 bits centered on the target bit X is greater than or equal to a certain number.
It is set to [0] only when is black, and set to [1] otherwise. In addition,
The value of K is the same as in the fourth embodiment.

As described above in detail with reference to the embodiments, since the present invention has a thinning circuit and a thickening circuit, it has the advantage that a hub turn with a substantially constant line width can be obtained without significantly distorting the original pattern χ. , it can be used in a preprocessing section of a handwritten character reading device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional preprocessing section, FIG. 2 is a diagram showing pattern distortion due to conventional line thinning, and FIG. 3 is a block diagram of a fixed line method according to the first embodiment of the present invention. 4 shows details of the thinning circuit in FIG. 3, FIG. 5 shows details of the thickening circuit in FIG. 3, and FIGS. 6 and 7 show details of the thinning circuit in FIG. 3. Explanatory diagram of constant line conversion in example, No. 8
The figure shows the thinning of diagonal lines in the first and second embodiments, FIG. 9 shows the line thinning when three stages of thinning circuit A are used, and FIG. It is a figure showing fixed line formation by a 3rd example. 4, 4-1 to 4-5... Binarized input signal obtained by photoelectric conversion, 5... Thinning circuit, 6...
... Thinning circuit output signal, 7... Inspection circuit, 8, 8-1 to 8-3... Thick line circuit control input signal, 9, 91 to 9-2. ...Thick circuit pattern input signal, 10...Thick hard circuit, 11...
... Fixed line output signal, 13-1 to 13-5, 14 to 1
〜14-5, 19-1〜19-3, 20-1〜20-3
, 21-1 to 21-2, 22...shift register, 15-1 to 15-24...exclusive OR circuit, 16-1 to 16-2...・Arithmetic circuit, 17・
...4AND circuit, 23...80R circuit, 24...0R circuit, XO~X24...
・Each bit output of shift registers 14-1 to 14-5,
CO-C8...Shift register 20-1-20
-3 bit output, PO... Bit output of shift register 22.

Claims (1)

[Claims] 1 Input a binary digital signal of a character figure and calculate i×i (i is an integer of 3 or more) centered on the bit of interest.
Detects the number of first change points from black to white or from white to black along the peripheral path of the bit, and detects j×j bits (j is an integer of 5 or more, and j ＞
Detecting the number of second changing points from black to white or from white to black along the peripheral path of i), and checking that at least the first number of changing points and the second number of changing points are one. If predetermined conditions including
A fixed line forming method characterized by carrying out thick line processing after carrying out the process one or more times.