JPS59143444A - Digital phase locked loop circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the use of a digital camera (DPI).
L) Regarding circuits, especially suitable for demodulating bipolar codes,
[Prior art] Fig. 1 shows a conventional DPL circuit used for initial tuning of a bipolar code.
The PLL circuit and the demodulation circuit, and FIG. 2 shows a signal time chart of each part of the first circuit. 8 in FIG. 1, 9 is a full-wave rectifier circuit, 10 is a slide→J-111 is a phase comparator, 14 is a 2N stage uptown counter 15 and a preset circuit 16
19 is a fixed frequency oscillator 2G,
A digital VCO 123 consisting of a pulse addition/removal circuit 21 and a frequency divider 22 is a delay element, and 24 is an identification circuit.

To explain the operation of the above-mentioned conventional circuit, suppose that the transmission data 1 shown in FIG. The signal is input to the full-wave rectifier circuit 9 as an input signal 3.

The output 4 of the full-wave rectifier circuit is sliced by a slicer 10 to become a phase comparison signal 5 and input to a phase comparator 11. The synchronizing signal 6 output from the digital VCO 19 is input to the phase comparator 11, and the phases of these two signals are compared every time the phase comparison signal 5 rises. If the synchronization signal 60 phase is ahead of the phase comparison signal 50 phase, a single pulse is outputted to the leading signal line 12, and if it is delayed, a single pulse is outputted to the lagging signal line 13. These two signal lines are connected to the up-count terminal and down-count terminal of a 2N-stage up/down counter 15, respectively, and when the phase continues to advance, the value of the counter increases, and when the phase continues to lag, it decreases.

When the phase difference is O, the lead signal line 12 and the delay signal line 13
Since the number of pulses generated in is the same in the long run, the value of the counter is a certain constant value (initial value==N.

N is an integer) and is increased or decreased in small steps. If the phase continues to advance, the counter value will slow down to a predetermined value of 2N at a certain point, and a carry signal 17 will be output. This carry signal 17 is passed through the preset circuit 16 to
The value of the N-stage amplifier down counter 15 is preset to a half value N. Conversely, if the phase continues to lag, the counter value will lag to 0 at a certain point, and a borrow signal 18 will be output. The borrow signal also presets the value of the 2N stage up/down counter to N via the preset circuit 16.

The pulse addition/removal circuit 21 supplies the output pulse 25 of the fixed frequency oscillator 20 as it is to the branching unit 22 when neither the carry signal 17 nor the borrow signal 18 is input. The frequency division ratio of the divider 220 is set so that the 60 cycles of the synchronization signal, which is the result of division, approximately matches the repetition cycle of the input signal 3. When the carry signal 17 is input, the pulse addition/removal circuit 21 thins out the output pulses 25 of the fixed frequency oscillator 20 and supplies them to the frequency divider 22, resulting in a 60-cycle length of the synchronization signal. On the other hand, when a borrow signal is input, another pulse is added to the output pulse 25 of the oscillator 207) and input to the frequency divider 22, so that the synchronization signal 60 period is controlled to be short.

The synchronization signal 6 obtained in this manner is delayed by a certain period of time τ by the delay g element 23, and then inputted as an identification pulse 7 to the identification circuit 24. The identification circuit 24 performs sumblinking on the full-wave rectified output 4 at the rising edge of the identification pulse 7, and outputs demodulated data 8 which is equal to redundant transmission data 1. Here, the delay time τ needs to be set so that the rising point of the identification pulse coincides with the point where the wave height of the full-wave rectified wave is the highest.

However, while I was thinking about it, I added 2 to the conventional DPL and L circuits mentioned above.
In this case, the base of the input signal 30 waveform may widen or shrink due to changes in the attenuation characteristics of the transmission path.

However, there was a problem in that the delay time τ had to be readjusted each time.

[Purpose of the invention]

The present invention has been made in order to solve the drawbacks of the above-mentioned conventional circuits, and is an improved digital phase locked loop (DPLL) that can generate identification pulses necessary for demodulating bipolar codes without adjustment. The purpose is to provide circuits.

[Summary of the invention]

In order to generate an identification pulse f in synchronization with the point in time when the wave height of the full-wave rectified waveform reaches its highest point, the phase comparator is used to determine when the input waveform reaches its highest point. It's good if you can separate it. The phase comparator cannot make the above judgment in real time, but at the end of one cycle of the input waveform, the start and end times of that cycle are known, and the highest point of the wave height is at the midpoint between the two times. Therefore, a phase comparator that can distinguish these two times may be used.

[Example of hakmoe]

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

In Figure 3, line numbers 9, 10, 15, 16, 20,
The portion consisting of circuit elements indicated by 21 and 22 has the same circuit configuration as in FIG. 26 is a rising edge detection circuit, 27 is a D-type flip-flop, and 28 and 29 are three-manufactured ANI) gates.

To explain the circuit operation of FIG. 3 above with reference to the signal waveform of FIG. 4, the rising edge detector 26 generates a set pulse 30 at the rising edge of the phase comparison signal 5, and sets the D-type flip-flop 27. , Q output = 1° q output = 0.

This output state is maintained until the identification pulse 7 rises, so from the rise of the phase comparison signal 5 to the rise of the identification pulse 7, the output pulse 25 of the fixed frequency excavator 20 is It is input to the down count terminal 31 of the 2N stage uptown counter 15. Next, when the identification pulse 7 rises, the output state of the D-type flip-flop 27 is inverted, and until the phase comparison signal 5 falls,
ANI) The pulse 25 is input to the up-count terminal 32 via the gate 29. While the phase comparison signal 5 is falling, both ANI gates are closed, so neither up-counting nor down-counting is performed. Here, the number of stages of the counter 150, 2N, counts up 25 output pulses while the phase comparison signal 5 is rising.
Alternatively, it is set to a value slightly larger than the value n to be counted down.

If the rising point of the identification pulse 7 is synchronized with the midpoint between the rising edge and the falling edge of the phase comparison signal 5, the value of the 2N stage anop down counter 5 changes before and after the rising edge of the phase comparison signal 5. There is no. However, if the phase of the identification pulse 70 is more advanced than the phase comparison signal 5, the down-counted value will be less than the around-counted value, so the value of the 2N-stage uptown counter 15 will increase. If the phase advances, the above value will further increase, and a carry signal 17 will be generated at a certain point. Conversely, if the phase continues to lag, a borrow signal 18 will be generated at a certain point.

The presetting operation of the 2N stage active down counter and the control of the digital VCO 19 using the carry signal 17 or the borrow signal 18 are the same as in the conventional DPLL circuit.

According to the above embodiment, the phase comparator of the DPLL circuit of the present invention includes the rising edge detection circuit 26, the D-type IJ block flop 27, the AND gate 28, the AND gate 29, and the DPLL circuit of the present invention.
The 2N-stage up-town counter 15 is composed of an N-stage r-turn counter 15, and also has a function as a filter circuit, and transmits the identification pulse synchronized with the midpoint between the rising and falling edges of the phase comparison signal 5 with a delay. Generate without elements.

[Effects of 6I3I)] As shown in the above ml and 71, according to the present invention, as in the conventional 1) PLL, the synchronization signal can be optimally identified using a delay element, etc. that generated the synchronization signal. Compared to the case where the identification pulse is generated by delaying it to a certain point, a delay element is not required, and accordingly, there is no need to adjust the delay time.

[Brief explanation of the drawing]

Figure M1 is a configuration diagram of a bipolar code demodulation circuit using a conventional DPLL circuit, Figure 2 is a signal time chart of each part of the above circuit, and Figure 3 is a configuration diagram of a bipolar code aA circuit to which a DPLL circuit according to the present invention is applied. , Figure 4 is the above 3rd figure.
FIG. 3 is a signal waveform diagram of the DPLL circuit shown in the figure. 1... Transmission data 2... Bipolar code 3.
・Input signal 4...Full wave'@flow ratio output wave...Phase comparison signal 6...Synchronization signal 7...Identification pulse
8... Demodulated data 9... All 11 rectifier circuits 10.
- Slicer 11... Phase comparator 12... Leading signal line 13... Lagging signal line 14... Filter circuit 15... 2N stage Atsufu town counter 16...
Preset circuit 17... Carry signal 18... Borrow signal 19... Digital V C020...
Fixed frequency oscillator 2] Pulse addition/removal circuit 22 -- Frequency divider 23 ・Boundary element 24 ・
-Identification circuit 25...Output pulse 26...Rise detection circuit 27...D-type flip-flops 28, 29...AND gate 30...Set pulse 31...Down count terminal 32... Upcount Terminal Representative Patent Attorney Akira Takahashi Ujiaki 3//Z

Claims (1)

[Claims] A fixed clock oscillator that generates a clock M times the frequency of the input signal, a 2N stage up/down counter that counts up or down from the initial 111N, and the M times lock is activated by the rising edge of the input signal. , connected to the up-count input of the 2N-stage up-down counter, and connected from the up-count input to the down-count input according to the rising edge of the synchronized clock to be generated,
It consists of an input clock inverter that stops counting at the falling edge of the input signal, and a synchronous clock generator that generates the synchronous clock by variably dividing the frequency of the M multiplier lock using a periodic control input. When the value of the 2N-stage up-down counter during downlink exceeds Ol or 2N, the value of the 2N-stage up-down counter is initialized to N using the pollo or carry signal. A digital phase clock droop circuit that synchronizes the synchronous clock to the midpoint between the rising and falling edges of the input signal by controlling the period of the generator.