JPS5914908B2 - Inner lead bonding equipment - Google Patents
Inner lead bonding equipmentInfo
- Publication number
- JPS5914908B2 JPS5914908B2 JP55126744A JP12674480A JPS5914908B2 JP S5914908 B2 JPS5914908 B2 JP S5914908B2 JP 55126744 A JP55126744 A JP 55126744A JP 12674480 A JP12674480 A JP 12674480A JP S5914908 B2 JPS5914908 B2 JP S5914908B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- heater
- inner lead
- chip
- lead bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/077—Connecting of TAB connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、バンプとフィンガをボンディングするテープ
キャリア方式のインナーリードボンディング装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tape carrier type inner lead bonding device for bonding bumps and fingers.
従来、テープキャリア方式によるインナーリードボンデ
ィングはつぎのように行なわれている。Conventionally, inner lead bonding using the tape carrier method has been performed as follows.
すなわち、シネフイルムのようなパーフォレーションを
持つたポリイミドテープに銅箔をラミネートし、これに
ボンディングワイヤに相当するリードパターンをホトエ
ッチでつくり、金または錫をめつきする。さらに、第1
図に示すように半導体チップ11にバンプ12を形成し
プレート13に設置する。そしてこのバンプ12にポリ
イミドテープ14と錫または金めつきされた銅箔で形成
されるテープキャリアのリード15を重ね合わせ、上か
らボンディングツール16で加圧加熱してボンディング
を行なつている。5 ところで、一般にインナーリード
ボンディングで用いられるのは、バンプ側もフィンガ側
も金を使用した金丸−金Au熱圧着方式と、バンプ側が
金でフィンガ側が錫めつきを使用した金Au−錫Sn共
晶方式である。That is, copper foil is laminated onto a polyimide tape having perforations similar to cine film, a lead pattern corresponding to a bonding wire is formed on this by photo-etching, and gold or tin is plated. Furthermore, the first
As shown in the figure, bumps 12 are formed on a semiconductor chip 11 and placed on a plate 13. Then, a polyimide tape 14 and a lead 15 of a tape carrier formed of tin or gold-plated copper foil are superimposed on the bump 12, and bonding is performed by applying pressure and heating from above using a bonding tool 16. 5 By the way, the two methods generally used for inner lead bonding are the gold round-gold Au thermocompression bonding method, which uses gold on both the bump side and the finger side, and the gold Au-tin Sn method, which uses gold on the bump side and tin plating on the finger side. It is a crystal method.
例えば後者の方式では、ボ10ンデイング時のボンディ
ングツール温度は大略Au−Sn共晶のできる温度、す
なわち217℃〜4180Cの範囲である。この高温の
ボンディングツールをバンプとフィンガの上から加圧し
てボンディングするのが普通である。15上述した構成
のボンディング装置では、ボンディングツールの熱が短
時間に小さなバンプを伝わつてチップ全体に広がるため
、バンフ丁の半導体チップのパッシベーション膜に熱が
原因のクラック等の不良を発生させる要因の一つとなる
。For example, in the latter method, the bonding tool temperature during bonding is approximately the temperature at which Au-Sn eutectic is formed, that is, in the range of 217°C to 4180°C. It is common practice to apply pressure to the bumps and fingers using this high-temperature bonding tool to perform bonding. 15 In the bonding equipment configured as described above, the heat from the bonding tool is transmitted through small bumps in a short period of time and spreads over the entire chip. Become one.
さら20に、第2図a、bに示すようにボンディング時
にAu−Sn共晶物ITが溶融して必要以外の場所に流
れ出し、短絡の原因となつてしまう等の欠点があつた。
本発明は上記の事情を考慮してなされたもので、25そ
の目的とするところは、ボンディング時の熱的ストレス
によるチップの不良発生を防止し、さらに共晶の溶融物
が必要以外の場所に流れ出ることによる不具合を減少で
きるインナーリードボンディング装置を提供することで
ある。Furthermore, as shown in FIGS. 2a and 2b, the Au-Sn eutectic IT melts during bonding and flows out to areas other than where it is needed, causing short circuits.
The present invention has been made in consideration of the above circumstances.25 Its purpose is to prevent the occurrence of chip defects due to thermal stress during bonding, and to prevent the eutectic melt from being disposed of in unnecessary locations. An object of the present invention is to provide an inner lead bonding device that can reduce problems caused by flowing out.
30以下、本発明の一実施例を図面を参照して説明する
。30, one embodiment of the present invention will be described below with reference to the drawings.
第3図aは本発明によるインナーリードボンディング装
置を示す図である。その構成は、タングステン等で形成
され、ボンディングツールと同程度の温度に設定される
第1のヒータ18がチ35ツプ11の支持体として設け
られ、その上にチップ11を囲むように枠状に形成され
た第2のヒータ19が、熱絶縁層20を介して設けられ
る。こ1り0−の第2のヒータ19はタングステン等で
形成され、図示するようにバンプ12より高く、ボンデ
イング時にその端部でフインガ15と接触してこのフイ
ンガ15を持ち上げるように構成される。FIG. 3a shows an inner lead bonding apparatus according to the present invention. The structure is such that a first heater 18 made of tungsten or the like and set at a temperature similar to that of the bonding tool is provided as a support for the chip 11, and a frame-shaped heater 18 is placed above the first heater 18 to surround the chip 11. A second heater 19 is provided with a thermal insulating layer 20 interposed therebetween. The second heater 19 is made of tungsten or the like, is higher than the bump 12 as shown, and is configured to come into contact with the finger 15 at its end and lift the finger 15 during bonding.
そして、このヒータ19は前記第1のヒータ18より低
い温度に加熱され、例えば、フインガが錫めつきの場合
には錫の融点、232℃より低い温度に設定するものと
する。上述のような第1および第2のヒータと熱絶縁層
で構成される加熱体を予め加熱しておき、第1のヒータ
18上にチツプ11を設置後、ボンデイングツール16
によりバンプ12とフインガ15を加圧加熱して共晶ボ
ンデイングを行なう。This heater 19 is heated to a temperature lower than that of the first heater 18. For example, if the fingers are tin-plated, the temperature is set to be lower than the melting point of tin, 232°C. The heating body composed of the first and second heaters and a thermal insulation layer as described above is heated in advance, and after installing the chip 11 on the first heater 18, the bonding tool 16 is heated.
The bump 12 and finger 15 are heated under pressure to perform eutectic bonding.
このときフインガ15は第3図bに示すように、この中
程21が第2のヒータ19によつて上に持ち上げられ、
先端部22が傾けられる。このような構成によれば、被
ボンデイング物のチツプがボンデイングツールと同程度
の温度に加熱されているため、ボンデイング時の熱によ
るパツシベーシヨン膜のクラツクなどの不良発生を防止
でき、ヒータでフインガを持ち上げて傾けることにより
、バンプとフインガの共晶の溶融物がチツプ上に流れ出
ることによる不具合を減少できるインナーリードボンデ
イング装置が得られる。At this time, as shown in FIG. 3b, the middle part 21 of the finger 15 is lifted upward by the second heater 19.
The tip 22 is tilted. With this configuration, the chip of the object to be bonded is heated to the same temperature as the bonding tool, so defects such as cracks in the passivation film due to heat during bonding can be prevented, and the fingers can be lifted by the heater. By tilting the inner lead bonding device, an inner lead bonding device is obtained in which problems caused by the eutectic melt of the bumps and fingers flowing out onto the chip can be reduced.
第1図は従来のインナーリードボンデイング装置を示す
図、第2図A,bはボンデイング不良を示す図、第3図
A,bは本発明の一実施例に係るインナーリードボンデ
イング装置を示す図、第4図は本発明装置によるボンデ
イング状態を示す図である。
11・・・・・・チツプ、12・・・・・・バンプ、1
4・・・・・・ポリイミドテープ、15・・・・・・フ
インガ、16・・・・・・ボンデイングツール 18・
・・・・・第1のヒータ、19・・・・・・第2のヒー
タ、20・・・・・・熱絶縁層。1 is a diagram showing a conventional inner lead bonding device, FIGS. 2A and 2B are diagrams showing bonding defects, and FIGS. 3A and 3B are diagrams showing an inner lead bonding device according to an embodiment of the present invention, FIG. 4 is a diagram showing a bonding state by the apparatus of the present invention. 11... Chip, 12... Bump, 1
4... Polyimide tape, 15... Finger, 16... Bonding tool 18.
...First heater, 19...Second heater, 20...Thermal insulation layer.
Claims (1)
装置において、被ボンディング物のチップを予めボンデ
ィングツールと同程度の温度に加熱する第1のヒータと
、チップを囲むように枠状に形成されて前記第1のヒー
タより低い温度に設定されこのヒータと熱絶縁層を介し
て設置された第2のヒータと、バンプとフィンガをボン
ディングするボンディングツールとを具備することを特
徴とするインナーリードボンディング装置。1. In a tape carrier type inner lead bonding apparatus, a first heater that heats a chip to be bonded in advance to a temperature similar to that of a bonding tool, and a first heater that is formed in a frame shape to surround the chip. An inner lead bonding device comprising: a second heater set at a lower temperature and installed through a thermal insulation layer from the heater; and a bonding tool for bonding a bump and a finger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55126744A JPS5914908B2 (en) | 1980-09-12 | 1980-09-12 | Inner lead bonding equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55126744A JPS5914908B2 (en) | 1980-09-12 | 1980-09-12 | Inner lead bonding equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5750440A JPS5750440A (en) | 1982-03-24 |
| JPS5914908B2 true JPS5914908B2 (en) | 1984-04-06 |
Family
ID=14942826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55126744A Expired JPS5914908B2 (en) | 1980-09-12 | 1980-09-12 | Inner lead bonding equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5914908B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727766Y2 (en) * | 1984-12-13 | 1995-06-21 | 株式会社豊田自動織機製作所 | Low-lift type vehicle handling speed control device |
-
1980
- 1980-09-12 JP JP55126744A patent/JPS5914908B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5750440A (en) | 1982-03-24 |
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