JPS59169247A - Synchronous switching system of digital radio circuit - Google Patents

Abstract

PURPOSE:To attain the synchronous switching over wide range of phase differences with no hit nor code error by securing a parallel transmission state when a radio circuit is switched and transmitting a spare circuit timing signal to a synchronous switch means after the synchronism is set up for the spare circuit timing. CONSTITUTION:A distribution circuit 11 contains a gate circuit which controls transmission and discontinuation of timing signals distributed to each using circuit and transmits usually no timing signal. When the using circuit is switched to a spare circuit, the digital signals 104 of the using circuit are transmitted in parallel by a control signal 101. Then the timing signal is sent to a synchronous switch circuit 12 by a control signal 105 after the transient due to the switching done by the spare digital signal 103 and then the synchronism is set up. In such a constitution, each using circuit has no fault owing to a step-out caused by a fault of the spare circuit or the transient produced during a switching mode. Thus it is possible to perform the synchronous switching over a wide range of phase differences with no hit nor code error.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous switching system for digital radio lines, and particularly to a digital radio communication system with an N:1 working/standby configuration in which a plurality of working radio lines correspond to one standby radio line. This paper relates to a synchronous switching method for digital radio lines that switches working and backup radio lines without momentary interruption and without code errors.

In recent years, in addition to analog information such as telephone voice, digital radio lines have increasingly been used to transmit data and other digital information. In switching methods using mechanical relays, which are conventionally used in analog wireless communication systems, the transition time of the relay cannot be ignored, and in the case of data transmission, code errors occur due to momentary interruptions and loss of synchronization associated with line switching. There is a problem with doing so.

Line switching in wireless lines is carried out when (a) an actual failure occurs in the working line due to a failure, propagation path abnormality, etc., and (→ preventive maintenance work is performed to maintain the working line, and in recent wireless lines, the latter is The number is overwhelmingly large.For this reason,
At least in the case (b), a synchronous switching system is required that can perform line switching without generating code errors, as proposed in, for example, Japanese Patent Laid-Open No. 143850/1983. This method is used as a switching device on the receiving side.
It uses a synchronous switching circuit consisting of an electronic circuit with a backup memory described in Publication No. 94709, and has the function of absorbing the transmission time difference between the working and standby radio lines and switching over uncoded error lines. There is. This transmission time difference is due to the propagation time difference (phase difference) due to the difference in the length of the signal line between the working and backup signal lines and fading in the radio section, and the phase difference (hereinafter referred to as phase difference) that can be absorbed by the synchronous switching circuit. ) is advantageous because the margin against fading increases and constraints on the wireless station configuration are relaxed. The phase difference that can be absorbed by the synchronous switching circuit described in the above-mentioned Japanese Patent No. 51-94709 is determined by the number of buffer memory stages υ used, and in order to increase this phase difference, it is necessary to increase the number of buffer memory stages. On the other hand, a synchronous switching circuit having a phase difference absorbing function capable of increasing the allowable phase difference with the same number of buffer memory stages has been proposed, for example, in Japanese Patent Laid-Open No. 55-88452. However, the synchronous switching circuit having this phase difference absorption function is
If the switching method described in Publication No. 850 is used as is, a failure will occur in the backup radio line as will be described later, which will adversely affect the working line and cause a code error, resulting in a simple problem in the switching circuit on the transmitting side. The disadvantage is that asynchronous switching circuits cannot be used.

An object of the present invention is to eliminate the above-mentioned drawbacks by adding a simple power control function, and to create a digital radio with an expanded allowable phase difference with the same number of buffer memory stages by using a synchronous switching circuit with a phase difference absorption function. This can be achieved by implementing a synchronous switching method for lines.

The synchronous switching method for digital wireless lines of the present invention is a synchronous switching method that instantaneously switches wireless lines using uncoded ib in a digital wireless communication system that has a plurality of working wireless lines and at least one backup wireless line between transmitting and receiving end stations. In the method, the transmitting end station is provided with a transmission switching means including a parallel transmission function for connecting and transmitting the digital signals transmitted on each of the working wireless lines in parallel to the backup wireless line, and the receiving end of each of the working wireless lines is connected to the backup wireless line. The synchronization switching means provided on the station side and switching between the working and backup radio lines without a coded error includes phase difference absorbing means for absorbing a phase difference between timing signals received and reproduced by the working and backup radio lines, respectively. , distributing means provided on the receiving terminal side of the protection radio line and distributing the data signal received and reproduced on the protection radio line and the protection line timing signal to each of the synchronization switching means; It has a control function for controlling sending and stopping, and when switching radio lines, the transmission switching means puts the working and backup radio lines into a parallel transmission state, and after establishing timing synchronization of the backup radio line, the protection line timing signal is switched to the synchronization state. It is configured by controlling the signal to be sent to the switching means.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a conventional digital radio line synchronous switching system described in Japanese Patent Application Laid-Open No. 55-143850, which is configured as follows. The input signal sent from the multiplexer (not shown) on the transmitting side is divided into two for the working line and the reserve line by the no-brid 1, and the standby side is sent to each transmitting signal processing circuit via a switch 2 using a relay. 3a, 3b
supplied to The transmission signal processing circuits 3a, 3b convert the bipolar signal used on the multiplexing device side into a unipolar signal used for code processing on the wireless device side, convert the speed of the code, and convert it into a bit for monitoring the wireless line. and frame synchronization bits. The digital signal into which these bits have been inserted is modulated by transmitters 4a+4b and sent as radio waves to the other station. On the protection line a side, a transmission switching circuit 5 composed of an electronic circuit connects a transmission signal processing circuit 3a and a transmitter 4.
a, and is configured to switch between active and standby in response to a control signal 101. The digital signals and regenerated timing signals (bit synchronization and frame synchronization) received and demodulated by the receivers 6a and 6b on the receiving end station side are applied to the synchronization switching circuit 7 on the working line side, and the output thereof is sent to the receiving end station. The signal processing circuit 8b performs inverse speed conversion to remove the wireless line monitoring bit, and then converts the signal into a bipolar signal, which is sent to a multiplexer (not shown) via a switch 9. The receiver output on the protection line a side is distributed by the distribution circuit 10 to the received signal processing circuit 8a and the synchronous switching circuit 7 of each working line, and the former is converted into a bipolar signal after reverse speed conversion and supplied to the switching device 9. , the latter is connected to the digital signal of the working line and the control signal 1 by each synchronous switching circuit 7.
02, the selection can be switched with no code error. When switching lines, first, control signal 1
01, the transmission switching circuit 5 is operated to disconnect the digital signal 103 that is always being sent to the protection line, and send the digital signal 104 of the working line to the working and protection lines in parallel. On the receiving side, after recovering the temporary synchronization error caused by switching the digital signal of the protection line, the control signal 102 is used to switch the readout path from the active and protection buffer memories of the synchronization switching circuit 7, thereby preventing uncoded errors. Line switching is completed. As mentioned above, this synchronous switching circuit 7 is a circuit described in Japanese Patent Application Laid-Open No. 51-94709, and has n stages of buffer memory for each of the working and backup data signals, and each data signal is read into the backup memory. By selectively reading out any of the decompressed data using a common read clock, synchronization switching without momentary interruption and without code error is performed. A more detailed explanation of this circuit will be omitted by referring to the above-mentioned publication if necessary, but the above-mentioned read clock is, for example, fixed at a certain time delay with respect to the bit synchronization timing signal on the working line side. The allowable phase difference between the signals on both lines is determined by the number of buffer memory stages. Oh, switch 2
and 9 are transmitting/receiving signal processing circuits 3al 3b and 8a,
This switching device is similar to that in the conventional analog system, which is provided for relief from device failures, including 8b, and has no direct relationship with the synchronous switching system described above.

The phase difference between the received signals on the working and protection lines is due to the phase fluctuation in the propagation path due to fading, the line length difference between the working and protection lines, that is, the transmission signal processing circuit 3b and the transmitter 4.
This is due to the difference in the length of the digital signal transmission line between the al 4b and the receivers 6a+6b and the synchronous switching circuit 7, and the difference in the length of the waveguide between the transmitter and receiver and the antenna. It is difficult to adjust the above-mentioned line length difference to zero for all N:1 working and protection lines, and the higher the speed of data transmission, the greater the effect, and the phase difference allowed by the synchronous switching circuit is larger. It is quite advantageous. For this reason, it is conceivable to use a phase difference absorption synchronous switching circuit that has a phase difference absorption function that can expand the allowable phase difference with the same number of buffer memory stages, but if the synchronous switching circuit 7 in Fig. 1 is replaced with the circuit described above, the following will be obtained. This results in significant drawbacks.

In the case of the synchronous switching circuit 7, the position of the read clock of the buffer memory is fixed to the current phase.
Even if the phase on the protection side fluctuates beyond the allowable range, synchronous switching becomes impossible, but signal transmission on the working line side is seriously hindered. In the phase difference absorption synchronization switching circuit, the position of the readout clock is controlled by both the working and standby phases and is moved by the average of the two, so the allowable phase difference becomes large, but the standby phase does not exceed the allowable value. If there is a large fluctuation beyond this limit, there is a drawback that an error occurs in reading from the buffer memory on the current side. Therefore, in the configuration shown in FIG. 1, if the backup line fails and the receiver 6a goes out of synchronization, the timing signal of the uncontrolled frequency of the synchronization regeneration oscillator in the receiver is supplied via the distribution circuit 10. There is a risk that a code error υ will occur on the working line. Furthermore, if the transmission switching circuit 5 on the transmitting side is switched asynchronously, the signals 103 and 10
Since there is a phase shift between the two, this sudden change causes a temporary loss of synchronization, which has the disadvantage of having a similar negative effect.

FIG. 2 is a block diagram of an embodiment of the present invention. The difference from FIG. 1 is that the distribution circuit 11 on the receiving side has n sets of outputs for distributing data and timing signals to each working line; It is constructed so that its sending and stopping can be controlled by a control signal 105, and is the same as in FIG. 1 except that the synchronous switching circuit 12 is the above-mentioned phase difference absorption synchronous switching circuit. The distribution circuit 11 includes a gate circuit that controls sending and stopping of the timing signal distributed to each working line, and normally does not send out timing signals, but when switching to the protection line, the control signal 101 is used to switch the timing signal from the working line to the working line. The digital signal 104 of the line is transmitted in parallel, and after the transient due to switching from the backup digital signal 103 is completed and synchronization (frame synchronization and bit synchronization) is established, the timing signal is transferred to the synchronization switching circuit 12 by the control signal 105.
It is controlled so that it is sent to With this configuration, each working line will not be affected by failures in the protection line or loss of synchronization due to transients during switching, and when switching, the phase difference absorption function allows the control signal 102 to be used over a wide phase difference range. Switching can be performed without momentary interruption or code error.

FIG. 3 is a block diagram of an embodiment of the synchronous switching circuit 12 shown in FIG.
An n-stage buffer memory 1J13.14 that sequentially reads and stores data signals 106, 107 from the data signals 1J13.14 and a bit synchronization timing signal synchronized with the frame synchronization timing signal 108.109 sent from the receiver 6a+6b at the same time as the data signal. A frequency divider 15.16 which divides the frequency of signals 110 and 111 by 1/2n, a buffer memory reading circuit 17.18 which sequentially reads out the contents of the buffer memory 13.14 using a common read signal, and a control signal 102 which outputs the output from the buffer memory 13.14.
It is comprised of a switching circuit 19 that performs selection switching in synchronization with the readout clock, and a readout signal generation circuit 20 that generates the above-mentioned common readout signal and has a phase difference absorbing function. This circuit uses a signal obtained by dividing the output of a voltage controlled oscillator 21 by 1/2n using a frequency divider 22 and delaying the phase by 90° using a 90° phase shifter 23, and a signal obtained by dividing the output of a voltage controlled oscillator 21 by 1/2n using a frequency divider 22 and delaying the phase by 90° using a 90° phase shifter 23. Comparing the phases with the frequency-divided output of i6 using phase comparators 24 and 25, synthesizing the outputs using a voltage synthesizer 26, and feeding them back to the voltage controlled oscillator 21 via an exclusive OR circuit 27 and a low-pass filter 28. controls the phase of the read signal. The circuit which is multi-branched before the 9σ phase shifter 23 and consists of the phase comparators 29 and 30, the voltage synthesizer 31, and the low-pass filter 32 does not have to be provided to speed up the synchronization pull-in time. . According to this circuit, when the phases of both the working and standby timing signals match, the phase of the read signal is equal to 90° of the 1/2n divided frequency wave, that is, each data of the buffer memory 1J13.14 having an n-stage configuration. The storage time is set to the middle of n bits, and if there is a phase difference, it is controlled back or forth by half of that amount, resulting in an allowable phase difference that is approximately twice as large as when it is fixed at one phase. For a more detailed explanation of this circuit, if necessary, please refer to the above-mentioned Japanese Patent Laid-Open No. 55-88452.

In the embodiment shown in FIG. 2, the distribution circuit 11 has n sets of outputs and is equipped with a timing signal sending control means, but the distribution circuit is the same as that shown in FIG. 2 may be provided with a control means for controlling reception of the protection line timing signal.

The data signal may be connected all the time, or the same effect can be obtained even if it is controlled simultaneously with the protection line timing signal. Also, in FIG. 2, the transmission switching circuit on the transmitting terminal side was explained as an asynchronous switching circuit consisting of an electronic circuit.
Working reserve digital signal 104. ．． If a synchronization switching circuit that synchronizes the timing of 103 before switching is used, switching to parallel transmission will not disturb the synchronization of the standby radio line. There is no problem even if it is sent to the synchronous switching circuit 12. Furthermore, in the above explanation, the removal of focus for radio line monitoring on the receiving side and the frequency inversion were explained as being performed in the received signal processing circuit 8b after the synchronization switching circuit 12 or 7, but there is no provision for frequency inversion. It is also possible to use a buffer memory with a synchronous switching function, and the distribution circuit can be provided after the monitoring bit is removed. In this case, in Figure 3, the frequency dividers 15 and 16 for reading the buffer memory, and the voltage controlled oscillator 21
It can be configured by selecting different values for the frequency division ratio of the frequency divider 22 that divides the output of the frequency divider 22. Although both FIGS. 1 and 2 show one radio section between the transmitting terminal station and the receiving terminal station, it goes without saying that the configuration may include intermediate relay stations. It is also clear that the same method can be applied even when there are two or more backup wireless lines.

As explained in detail above, according to the synchronous switching method for digital wireless lines according to the present invention, a phase difference absorbing synchronous switching circuit that can expand the allowable phase difference with the same number of buffer memory stages as the conventional method is used to reduce transients during switching. It is possible to provide a synchronous switching method that is not adversely affected by failures of backup wireless lines or backup radio lines, increases the margin against fading, and eases construction constraints.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example of a synchronous switching system for digital wireless lines, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of an embodiment of a synchronous switching circuit having a phase difference compression function. 1...Hybrid, 2,9-...Switcher, 3a. 3b...Transmission signal processing circuit, 4a14b...
...Transmitter, 5...Transmission switching circuit, 6a+6
b...Tune receiver, 7゜12...Synchronization switching circuit,
Ba, Bb... Reception signal processing circuit, 10.11
...Distribution circuit, 13.14...Buffer memory, 15, 16.22... Frequency divider, 17
．． 18...Buffer memory read circuit, 19
...Four switching circuit, 20... Read signal generation circuit, 21... Voltage controlled oscillator, 23...
・90' phase shifter, 24, 25° 29.30...
Phase comparator, 2 (i, 31...Four voltage synthesis circuit, 27
...Exclusive OR circuit, 28.32...Song low-pass filter.

Claims (1)

[Claims] In a synchronous switching method of a digital wireless communication system having a plurality of working radio lines and at least one backup radio line between transmitting and receiving end stations, in which wireless lines are switched instantaneously without coded errors, the transmitting end station switches between each of the working radio lines. It is equipped with a transmission switching means including a parallel transmission function that connects and transmits digital signals transmitted over the line to the backup radio line in parallel; The synchronization switching means for switching wireless lines without coded errors includes phase difference absorbing means for absorbing a phase difference between timing signals received and reproduced on the working and backup radio lines, respectively, and the receiving end of the backup wireless line A distribution means provided on the station side and distributing the data signal received and reproduced on the backup radio line and the backup line timing signal to each of the synchronization switching means has a control function that controls at least sending and stopping of the backup line timing signal. When switching wireless lines, the transmission switching means puts the working and protection radio lines into a parallel transmission state, and controls the protection line timing signal to be sent to the synchronization switching means after timing synchronization of the protection radio lines is established. A synchronous switching method for digital wireless lines characterized by the following.