JPS5918656A - Manufacture of substrate for integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an insulated and isolated Si island by a method wherein a poly Si is superposed on a single crystal Si substrate via an Si3N4, and the Si substrate is partially changed into porous state and oxidized. CONSTITUTION:The Si3N4 11, SiO2 12 (omissible), and poly Si 13 are deposited on the N type single crystal Si substrate 10. After polishing the Si substrate 10, P layers which reach the Si3N4 are provided by applying an Si3N4 mask 14. The exposed single crystal Si and the lower side thereof are changed porous down to the Si3N4 by anodic formation in HF. Successive oxidation causes to form SiO2 15 with approximately the same area as the porous parts, and accordingly single crystal islands 10' are completed. This constitution unnecessitates V-grooves, therefore the orientation of crystal surfaces of the substrate is not restricted, and then element formation can be performed by utilizating every crystal surface. Since grooves are not formed, the generation of warpage and damage decreases.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an integrated circuit substrate using dielectric isolation, and in particular, a method for forming silicon oxide that recesses single-crystal silicon islands that serve as isolation regions. It is related to.

There are various methods for isolating elements in semiconductor integrated circuits, but FN junction isolation is commonly used in Rt mode. However, in recent years, the use of U electric insulation isolation has been considered because it is superior to PN junction isolation in terms of characteristics such as withstand voltage, capacity, speed, and leakage.

However, in this dielectric insulation separation, the number of man-hours increases and the yield decreases, which are major problems in terms of generalization.

The most commonly used dielectric insulation isolation technology involves forming a V-shaped groove in a silicon substrate, forming an oxide film on the groove, and then depositing polycrystalline silicon fc about 400 μm thick at a temperature close to 1200°C.
It is being deposited. There is a problem that the wafer may warp or be damaged due to the heat generated at this time, and because of this, when polishing the silicon ribbon substrate, islands of single crystal silicon cannot be formed as designed, resulting in excessive polishing, or the bottom of the groove is In many cases, it cannot be scraped off and is not completely separated.

Consideration has also been given to methods for solving the problems in dielectric isolation technology as described above. One is to reduce the warpage of the wafer even when polycrystalline silicon is deposited. Another method attempts to form dielectric isolation regions without forming trenches. Regarding such technology, please refer to Japanese Patent Application Laid-open No. 53-707.
However, these methods require a large number of man-hours, which is disadvantageous in terms of cost and yield.Also, the oxidation for forming the dielectric material is not sufficiently performed, resulting in dielectric insulation. There are problems such as not being able to take full advantage of the characteristics of separation.

The present invention solves the above-mentioned problems and provides a manufacturing method capable of obtaining an integrated circuit board using dielectric insulation separation with high reliability and excellent characteristics with an extremely small number of man-hours. purpose.

In the method for manufacturing an integrated circuit substrate according to the present invention, the above object is achieved by partially oxidizing single crystal silicon, and furthermore, an oxide film between the crystal silicon and the polycrystal silicon is removed. It can be oxidized without attacking polycrystalline silicon or polycrystalline silicon.

Embodiments of the present invention will be described below with reference to the drawings.

Drawings (A-F) are front sectional views showing embodiments of the invention.

A layer 11 of nitrous silicon (5iaNa) is formed to a thickness of about 200 to 2000 mm on one side of a single crystal silicon substrate 10 (A).

A film 12 of silicon dioxide S1a2 is formed on the film 11 of 01aN4 to a thickness of 400υ to 800Qλ (successfully).

These nitride film 11 and oxide film 12 are used as dielectrics to separate elements, but the oxide film does not necessarily need to be formed. Nitride films and oxide films are usually formed by vapor phase growth.

When silicon is vapor phase grown on the surface of the film 12 of Elio2, polycrystalline silicon 13 is formed. The polycrystalline silicon 13 is formed to have a thickness sufficient to support a silicon wafer, for example, e is about 40011 m in the case of a 6-inch wafer (C1).

The single crystal silicon substrate 10 is polished from the back side to a thickness such that FC'>H for forming an integrated circuit element. Usually 5~
It shall be within 50 μm. Apply silicon nitride (8L) to the polished surface.
-sr4) film 14 is formed, and only the portion that will become the separation region is removed by etching (tin).

This nitride film 14 serves as an i-layer for forming an isolation region, and is preferably formed in such a way that an area of single crystal silicon 10 smaller than the area of the isolation region is exposed.

Next, using the nitride film 14 as a mask, P-type impurities are implanted or diffused into the single crystal silicon 10 to form a P-type region reaching the nitride film 11 from the surface.
The mold region may be diffused from both sides of the single crystal silicon. However, if other means are used in conjunction with F.
The plastic impurity is not necessarily implanted or diffused, and the next process may proceed to the N-type t.

In a state βk where the nitride film 14 is partially formed on the surface of the single crystal silicon substrate 100, the single crystal silicon substrate 10 is anodized in hydrogen fluoride (HF).

By this anodization, the exposed single-crystal 7-licon and its lower portion become porous silicon. In this case, if a P-shaped region is formed, anodization becomes easy. The porous silicon is formed so as to reach from the surface to the nitride film 11 on the opposite side.

Porous silicon has the property of being easily oxidized, so when a wafer on which porous silicon is formed is oxidized, the porous silicon portion progresses to oxidation and changes to silicon oxide 15 (Takumi. 15 is formed in a portion corresponding to the porous silicon with the same area as y.It is insulated from the oxide film 12 formed first by 7,3. Islands 1υ of single-crystal silicon are formed.

Finally, the nitride film 14t is removed to form an integrated circuit substrate.

Note that the oxide layer 12 is not necessarily necessary, and only a nitride film may be used to separate exposed silicon and polycrystalline silicon.

As described above, in the method for manufacturing an integrated circuit substrate according to the present invention, a single crystal is formed by forming a pre-formed insulating layer containing a 7 arsenic nitride film, a silicon oxide formed by oxidizing porous silicon, and ζ. Islands of silicon are formed to be isolated by a J iJ body layer. Therefore, it is only necessary to form porous silicon in the range from the window of the silicon nitride film to the nitride film formed on the oxide film. In addition, since the nitride film is formed between the oxide film and the single crystal silicon, the oxide film or polycrystalline silicon will not be attacked during anodization, and no As mentioned above, only the area that is to be anodized becomes porous silicon. However, the size of the window formed in the silicon nitride film is made smaller than the area of the region to be made porous. This is because the material expands in the lateral direction when the P-type region is formed or when it is made porous by anodization.

According to the method for manufacturing an integrated circuit board according to the present invention, there is no need to form grooves on the board, so there is less risk of warping or damage to the board. In addition, even if the substrate warps, the time is adjusted so that the deepest part of the substrate is anodized.This ensures that the substrate becomes porous and prevents the formation of oxides. It becomes possible. Therefore,
The conventional problem of not being able to form an insulating separation layer all the way to the surface due to substrate warping is solved. Therefore, the yield in the manufacturing process is significantly improved.

Furthermore, since the nitride film can prevent unnecessary anodization and erosion, there is also the advantage that the reliability of the device can be improved. Using a nitride film and an oxide film together is advantageous in that capacity can be reduced and differences in thermal expansion coefficients can be alleviated.

According to the present invention, there is no need to form a 7-shaped groove, so the orientation of the crystal plane of the substrate is not restricted, and an element can be formed using any crystal plane. In addition, as a substrate material for dielectric separation, regardless of the product type, it can be stocked after completing the above-mentioned 0 process, which is advantageous in terms of manufacturing by shortening the number of process days and controlling quantity.

[Brief explanation of drawings]

The drawing shows a front sectional view of an embodiment of the invention. 11...Nitride film, 12...Oxide film. 14... Nitride film patent applicant Automatic Measurement Technology Research Association Procedural Amendment (Method) 6゜ Japan Patent Office Commissioner Kazuo Wakasugi 1. Indication of the case Patent Application No. 127226 of 1982 2. Collection of names of inventions Manufacturing method for circuit boards 3, Relationship with the case of the person making the amendment Patent applicant representative Takashi Sugiyama 4, Subject of amendment by agent (1) Brief explanation column of drawings in the specification (2) Amendment of drawings Contents (1) The brief explanation column of drawings in the specification will be corrected as follows. [4. Brief Description of the Drawings FIG. 1 (A-p) shows a front sectional view of an embodiment of the present invention. 11...Nitride film, 12...Oxide film. 14...Nitride film'' (2) Correct the drawing as shown in the attached sheet.

Claims (2)

[Claims] (1) Form a silicon nitride film on one surface of a single-crystal silicon substrate, form a polycrystalline silicon layer on the silicon nitride film, polish the single-crystal silicon substrate from the back side to a predetermined thickness, and polish A part of the surface of the single-crystal silicon substrate is covered with a nitride film, and the single-crystal silicon is heated in hydrogen fluoride using the nitride film as a mask. By anodizing the silicon to make it partially porous and oxidizing the silicon, which has become foliated, multiple islands of single-crystal silicon surrounded and isolated by silicon oxide are formed. 1. A method for manufacturing an integrated circuit substrate, comprising: forming a substrate for an integrated circuit; (2) The single crystal silicon substrate is of N type conductivity type, and after covering a part of the surface of the polished single crystal silicon substrate with a nitride film, the nitride film is used as a mask to conduct P type conductivity type. is formed on the single-crystal silicon substrate, and using the nitride film as a mask, the P-type region of the single-crystal silicon substrate is anodized in hydrogen fluoride to partially make it porous. A method for manufacturing an integrated circuit substrate according to claim 1.