JPS59189355U - Reception input circuit of FM receiver - Google Patents
Reception input circuit of FM receiverInfo
- Publication number
- JPS59189355U JPS59189355U JP8208083U JP8208083U JPS59189355U JP S59189355 U JPS59189355 U JP S59189355U JP 8208083 U JP8208083 U JP 8208083U JP 8208083 U JP8208083 U JP 8208083U JP S59189355 U JPS59189355 U JP S59189355U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- input signal
- received input
- circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＦＭラジオ受信機のフロントエンド部を
示す構成説明図、第２図ａおよび第２図すは第１図の受
信入力回路の弱入力時および強入力時の動作特性を示す
特性図、第３図は本考案の一実施例に係るＦＭラジオ受
信機のフロントエンド部を示す構成説明図、第４図ａお
よび第４図すは第３図の受信入力回路の弱入力時および
強入力時の動作回路を示す回路図、第５図ａおよび第５
図すはそれぞれ第４図ａおよび第４図すの動作回路に対
応する動作特性を示す特性図である。
５・・・〜ＡＧＣ回路、１１・・・・・・受信同調回路
、１４・・・・・・電源線、３１・・・・・・第１のト
ランジスタ、３２・・・・・・第２のトランジスタ、３
３． ３４． ３５・・・・・・抵抗、３７・・・・・
・バイアス制御用トランジスタ。Fig. 1 is a configuration explanatory diagram showing the front end section of a conventional FM radio receiver, and Figs. 2a and 2 show the operating characteristics of the receiving input circuit of Fig. 1 at weak input and strong input. Characteristics diagram, FIG. 3 is a configuration explanatory diagram showing the front end section of an FM radio receiver according to an embodiment of the present invention, and FIG. 4a and FIG. and circuit diagrams showing the operating circuit at the time of strong input, Figures 5a and 5.
4A and 4B are characteristic diagrams showing operating characteristics corresponding to the operating circuits of FIGS. 4A and 4S, respectively. 5...AGC circuit, 11...Reception tuning circuit, 14...Power line, 31...First transistor, 32...Second transistor, 3
3. 34. 35...Resistance, 37...
・Bias control transistor.
Claims (2)
幅用の第１のトランジスタおよび第２のトランジスタを
並列に設け、受信入力信号レベルが小さい弱入力時であ
るか受信入力信号レベルが大きい強入力時であるかに応
じてＡＧＣ電圧によって前記第１のトランジスタおよび
第２のトランジスタを選択して使用し、かつこの選択使
用するトランジスタにＡ級動作点を与えるように回路形
成してなることを特徴とするＦＭ受信装置の受信入力回
路。(1) A first transistor and a second transistor for high-frequency amplification are provided in parallel to amplify each received input signal, and the received input signal level is weak when the received input signal level is low, or the received input signal level is high when the received input signal level is high. The first transistor and the second transistor are selected and used according to the AGC voltage depending on the time, and the circuit is formed so as to give a class A operating point to the selected transistor. A receiving input circuit for an FM receiving device.
１のトランジスタのエミッタに接続され、この第１のト
ランジスタのコレクタに前記第２のトランジスタのコレ
クタが接続きれ、この接続点と電源線との間に受信同調
回路が接続され、前記第２のトランジスタのエミッタは
所定抵抗を介して第１のトランジスタのエミッタに接続
され、第１のトランジスタのエミッタと接地端との間に
抵抗が接続され、第１のトランジスタのベースは前記電
源線に接続されると共にＡＧＣ回路出力電圧がベースに
印加されるバイアス制御用のトランジスタを介して接地
され、第２のトランジスタのベースは前記電源線に接続
されてなることを特徴とする前記実用新案登録請求の範
囲第１項記載のＦＭ受信装置の受信入力回路。(2) The received input signal is connected to the emitter of the first transistor via a coupling capacitor, the collector of the first transistor is connected to the collector of the second transistor, and this connection point is connected to the power supply line. A reception tuning circuit is connected between the transistors, the emitter of the second transistor is connected to the emitter of the first transistor via a predetermined resistor, and a resistor is connected between the emitter of the first transistor and a ground terminal. , the base of the first transistor is connected to the power line and grounded via a bias control transistor to which the AGC circuit output voltage is applied to the base, and the base of the second transistor is connected to the power line. The receiving input circuit for an FM receiving device according to claim 1, characterized in that the receiving input circuit comprises:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8208083U JPS59189355U (en) | 1983-05-31 | 1983-05-31 | Reception input circuit of FM receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8208083U JPS59189355U (en) | 1983-05-31 | 1983-05-31 | Reception input circuit of FM receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59189355U true JPS59189355U (en) | 1984-12-15 |
Family
ID=30212031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8208083U Pending JPS59189355U (en) | 1983-05-31 | 1983-05-31 | Reception input circuit of FM receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59189355U (en) |
-
1983
- 1983-05-31 JP JP8208083U patent/JPS59189355U/en active Pending
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