JPS59189773U - Automatic pause setting circuit - Google Patents

Automatic pause setting circuit

Info

Publication number
JPS59189773U
JPS59189773U JP8336283U JP8336283U JPS59189773U JP S59189773 U JPS59189773 U JP S59189773U JP 8336283 U JP8336283 U JP 8336283U JP 8336283 U JP8336283 U JP 8336283U JP S59189773 U JPS59189773 U JP S59189773U
Authority
JP
Japan
Prior art keywords
setting circuit
automatic pause
pause setting
automatic
recording medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8336283U
Other languages
Japanese (ja)
Inventor
晃 武田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8336283U priority Critical patent/JPS59189773U/en
Publication of JPS59189773U publication Critical patent/JPS59189773U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、コンパクトディスクシステムの信号フォーマ
ットを示す図、第２図は本考案に係る自動ポーズ設定回
路を示す図、第３図は動作波形図である。 ６は積分回路、７はワンショット回路（ポーズ状態設定
信号の作成回路）、Ｓはポーズスイッチ、８はシステム
コントロール用マイクロプロセッサ、９はキーマトリッ
クス入力部。FIG. 1 is a diagram showing a signal format of a compact disc system, FIG. 2 is a diagram showing an automatic pause setting circuit according to the present invention, and FIG. 3 is an operation waveform diagram. 6 is an integration circuit, 7 is a one-shot circuit (pause state setting signal generation circuit), S is a pause switch, 8 is a system control microprocessor, and 9 is a key matrix input section.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）記録媒体に記録された情報と情報の間を示す信号
に関連してポーズ状態設定信号を作成する回路を設けた
ことを特徴とする自動ポーズ設定回路。(1) An automatic pause setting circuit comprising a circuit for creating a pause state setting signal in relation to a signal indicating a difference between pieces of information recorded on a recording medium. （２）記録媒体に記録された情報が音楽面であることを
特徴とする実用新案登録請求の範囲第１項記載の自動ポ
ーズ設定回路。(2) The automatic pause setting circuit according to claim 1, wherein the information recorded on the recording medium is a music surface.
JP8336283U 1983-05-31 1983-05-31 Automatic pause setting circuit Pending JPS59189773U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8336283U JPS59189773U (en) 1983-05-31 1983-05-31 Automatic pause setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8336283U JPS59189773U (en) 1983-05-31 1983-05-31 Automatic pause setting circuit

Publications (1)

Publication Number Publication Date
JPS59189773U true JPS59189773U (en) 1984-12-15

Family

ID=30213321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8336283U Pending JPS59189773U (en) 1983-05-31 1983-05-31 Automatic pause setting circuit

Country Status (1)

Country Link
JP (1) JPS59189773U (en)

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