JPS59201548A - Bus changeover control system - Google Patents
Bus changeover control systemInfo
- Publication number
- JPS59201548A JPS59201548A JP58075470A JP7547083A JPS59201548A JP S59201548 A JPS59201548 A JP S59201548A JP 58075470 A JP58075470 A JP 58075470A JP 7547083 A JP7547083 A JP 7547083A JP S59201548 A JPS59201548 A JP S59201548A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- common bus
- switching
- panels
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はストアード・プログラムおよびマイクロコンピ
ュータから構成され、システムの制御を司さどる制御盤
と、相手局に対しデータの送受信を行う複数台の送受信
盤と、それらを接続する共通バスとからなる制御装置に
おけるバス切替制御方式に関する。[Detailed Description of the Invention] The present invention is composed of a stored program and a microcomputer, and connects a control panel that controls the system, a plurality of transceiver panels that transmit and receive data to and from partner stations, and a control panel that controls the system. This invention relates to a bus switching control method in a control device comprising a common bus.
従来、この種の制御装置におけるバス、割込信号線の障
害検出および切離しを行う回路はバスにおける障害の場
合には検出時点でバスにアクセスしている送受信盤を障
害発生源と判断し、バスに対しインピーダンスが極めて
高くなるような制御信号をその送受信盤に送出していた
。Conventionally, in this type of control device, the circuit that detects and disconnects bus and interrupt signal line failures determines that the transmitter/receiver board that is accessing the bus at the time of detection is the source of the failure, and disconnects the bus and interrupt signal lines. A control signal with an extremely high impedance was sent to the transmitter/receiver panel.
この制御方法は送受信盤の障害発生箇所がバスに直接接
続されていない部分であるときは確実に障害発生送受信
盤をバスより切離すことができ、捷だ制御装置のバスも
１系統で充分である。This control method makes it possible to reliably disconnect the faulty transmitting/receiving board from the bus when the fault occurs in a part of the transmitting/receiving board that is not directly connected to the bus, and one bus system for the switched control device is sufficient. be.
しかし、障害発生箇所がバスに直接接続されている部分
のときには障害検出盤から制御信号を送出してもバスの
状態が固定化されるので、制御盤と障害発生以外の送受
信盤との間のバスを経由したデータ送受が不能となり、
その結果、制御装置の機能が完全に停止するという欠点
があった。However, if the fault occurs in a part that is directly connected to the bus, the bus status is fixed even if the fault detection board sends a control signal. Data transmission and reception via the bus becomes impossible,
As a result, there was a drawback that the function of the control device was completely stopped.
本発明の目的に複数の送受信盤のうちの１台にバスの状
態を固定化する障害が発生しても他の送受信盤と制御盤
との間のデータの送受信を可能にし、システムの完全停
止を防止することのできる制御装置におけるバス切替制
御方式を提供することにある。The purpose of the present invention is to fix the bus status in one of a plurality of transmitting/receiving boards.Even if a failure occurs, data can be sent and received between the other transmitting/receiving boards and the control board, and the system can be completely stopped. An object of the present invention is to provide a bus switching control method in a control device that can prevent the above.
前記目的を達成するために本発明ＩＣよるバス切替制御
方式はデータの送受信をするための複数台の送受信盤と
、前記複数の送受信盤を制御する制御盤と、共通バスの
接・断を行うための複数の切替盤と、パリティ・エラー
を検出するためのパリティ検出部とを含み、前記制御盤
に接続される共通バスは２系統に分割してそれぞれの系
の共通バスに前記切替盤を接続し、さらに前記各切替盤
に接続される共通バスにそれぞれ前記複数の送受信盤を
接続し、切替盤を接にすることにより、一方の系の共通
バスによって前記制御盤と複数の送受信盤を接続し、複
数の送受信盤のうち１以上に障害が発生した場合、前記
パリティ検出部によって前記切替盤を断とすることによ
って複数の送受信盤を前記一方の系の共通バスより切離
し、他方の系の共通バスによって前記制御盤と複数の送
受信盤を接続するように構成しである。In order to achieve the above object, the bus switching control system using the IC of the present invention connects/disconnects a plurality of transmitting/receiving panels for transmitting and receiving data, a control panel controlling the plurality of transmitting/receiving panels, and a common bus. The common bus connected to the control panel is divided into two systems, and the switching board is connected to the common bus of each system. By connecting the plurality of transmitting/receiving panels to a common bus connected to each of the switching panels, and connecting the switching panels, the control panel and the plurality of transmitting/receiving panels can be connected via the common bus of one system. If a failure occurs in one or more of the plurality of transceiver panels, the parity detection section disconnects the plurality of transceiver panels from the common bus of one system by disconnecting the switching board, and disconnects the plurality of transceiver panels from the common bus of the one system. The control panel and the plurality of transmitter/receiver panels are connected through a common bus.
前記構成によれば送受信盤１台の障害でシステム全体が
ダウンすることを防止でき、本発明の目的に完全に達成
できる。According to the above configuration, it is possible to prevent the entire system from going down due to a failure in one transceiver board, and the object of the present invention can be completely achieved.
以下、本発明を添付図面より詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.
第１図は本発明によるバス切替制御方式の実施例を示す
図である。FIG. 1 is a diagram showing an embodiment of a bus switching control system according to the present invention.
第１図において点線で囲んだ部分はバス切替回路であり
、同一の回路構成をもつ４台の切替盤（ＳＷ−ＩＡ、５
Ｗ−２Ａ、５Ｗ−ＩＢ、５Ｗ−２Ｂ）によって構成され
ている。Ｃ０ＮＴ １およびＣ０ＮＴ２１−ｊともに同
一のマイクロ・プロ叱ツサとストアード・プログラムそ
の他で構成された制御盤であり、制御装置の全体動作は
この二重化さ力５た一方の制御盤によって制御される。In Figure 1, the part surrounded by dotted lines is the bus switching circuit, and four switching boards (SW-IA, 5
W-2A, 5W-IB, 5W-2B). Both C0NT1 and C0NT21-j are control panels composed of the same micro processor, stored programs, etc., and the overall operation of the control device is controlled by one of the duplicated control panels.
ＢＵＳ−１は制御盤Ｃ０ＮＴ １がら延びた第１の共通
バスであり、切替盤５Ｗ−ＩＡによって共通バスＢＵＳ
−Ａとの接続が接・断され、切替盤５Ｗ−ＩＢＫよって
共通バスＢＵ８−Ｂとの接続が接・断される。ＢＵＳ−
２は制御盤Ｃ０ＮＴ２から延びた第２の共通バスであり
、共通バスＢＵＳ−ＡおよびＢＵＳ−Ｂとの接続１ｌ−
Ｉ第１の共通バスＢＵＳ−１の場合と同様に共通バスＳ
Ｗ −２Ａおよび５Ｗ−２Ｂによって行われる。ＴＲ
Ｉ〜ＴＲｎは送受信盤でありバス切替の効果を生かすた
めにそれぞれ共通バスＢＵ８−ＡとＢＵＳ−Ｂに接続さ
れている。BUS-1 is the first common bus extending from the control panel C0NT1, and the common bus BUS-1 is connected to the common bus BUS by the switching panel 5W-IA.
-A is connected/disconnected, and the switching board 5W-IBK connects/disconnects the common bus BU8-B. BUS-
2 is a second common bus extending from the control panel C0NT2, and is connected to the common buses BUS-A and BUS-B.
I As in the case of the first common bus BUS-1, the common bus S
Performed by W-2A and 5W-2B. T.R.
I to TRn are transmitting/receiving boards, and are connected to common buses BU8-A and BUS-B, respectively, in order to take advantage of the effect of bus switching.
Ｔは共通バスの終端盤であり、共通バスＢＵＳ−Ａまた
ばＢＵＳ−Ｂを低インピーダンスで終端するとともに、
制御盤Ｃ０ＮＴ１またはＣ０ＮＴ２が共通バス上に出力
したデータのパリティ・エラーを検出する機能も持って
おり、検出結果は信号線１３によって切替盤８Ｗ−ＩＡ
およびＳ Ｗ −２Ａに伝達され、信号１４によって切
替盤５Ｗ−ＩＢおよび５Ｗ−２Ｂに伝達される。ＯＰは
二重化された制御盤のうち一方を運用状態にし、他方を
待機状態にする操作盤で、信号線１１の出力が制御盤Ｃ
０ＮＴ １、切替盤５Ｗ−ＩＡおよび５Ｗ−２Ａに伝達
されておゆ、信号線ｌ！２の出力が制御盤Ｃ０Ｎｉ’２
、切替盤Ｓ Ｗ −２Ａおよび５Ｗ−２Ｂに伝達される
。T is a common bus termination board, which terminates the common bus BUS-A or BUS-B with low impedance, and
It also has a function to detect parity errors in the data output by the control panel C0NT1 or C0NT2 onto the common bus, and the detection results are sent to the switching panel 8W-IA via the signal line 13.
and SW-2A, and is transmitted by signal 14 to switchboards 5W-IB and 5W-2B. OP is an operation panel that puts one of the duplicated control panels into the operating state and the other into the standby state, and the output of the signal line 11 is connected to the control panel C.
0NT 1, transmitted to switchboards 5W-IA and 5W-2A, signal line l! 2 output is control panel C0Ni'2
, is transmitted to the switching boards SW-2A and 5W-2B.
操作盤ＯＰによって制御盤Ｃ０ＮＴ １が運用で制御盤
Ｃ０ＮＴ ２が待機のときには、切替盤５Ｗ−ＩＡが第
１の共通バスＢＵＳ−１と共通バスＢＵＳ−Ａを、切替
盤５Ｗ−ＩＢが第１の共通バスＢ Ｕ Ｓ −１と共通
バスＢＵＳ−Ｂを接続しており、切替盤５Ｗ−２Ａが第
２の共通バスＢＵＳ−２から共通バスＢＵＳ−Ａを、切
替盤５Ｗ−２Ｂが第２の共通バスＢＵＳ−２から共通バ
スＢＵ Ｓ−Ｂを分離している。When the control panel C0NT 1 is in operation and the control panel C0NT 2 is in standby mode due to the operation panel OP, the switching panel 5W-IA connects the first common bus BUS-1 and the common bus BUS-A, and the switching panel 5W-IB connects the first common bus BUS-1 and the common bus BUS-A. The common bus BUS-1 and the common bus BUS-B are connected, and the switch board 5W-2A connects the common bus BUS-A from the second common bus BUS-2, and the switch board 5W-2B connects the common bus BUS-A from the second common bus BUS-2. The common bus BUS-B is separated from the common bus BUS-2.
第２図は切替盤の詳細ブロックである。共通バスＢ１に
第１図の第１の共通バスＢＵＤ−１ｔたは第２の共通バ
スＢＵＳ−２に対応し、共通バスＢ２は共通バスＢｕｓ
−ＡまたはＢＵＳ−Ｂに対応している。ＰＤはバス上の
データの方向が共通バスＢ２から共通バスＢ１のとき（
第１図では制御盤Ｃ０ＮＴ １またにＣ０ＮＴ２が送受
信盤ＴＲＩ〜ＴＲｎの１台からデータを読取る動作）、
共通バスＢ１におけるパリティ・エラーの有・無を検出
するパリティ検出回路であり、検出結果は信号線１５に
よって論理積回路Ｇ１に伝達される。信号線１６は第１
図における信号線Ｚ３ｔたｔｌ’ｌ１４に対応するもの
である。FIG. 2 is a detailed block diagram of the switching board. The common bus B1 corresponds to the first common bus BUD-1t or the second common bus BUS-2 in FIG.
-A or BUS-B. When the direction of data on the bus is from common bus B2 to common bus B1, PD is
In Fig. 1, the control panel C0NT1 or C0NT2 reads data from one of the transmitter/receiver panels TRI to TRn).
This is a parity detection circuit that detects the presence or absence of a parity error on the common bus B1, and the detection result is transmitted to the AND circuit G1 via the signal line 15. The signal line 16 is the first
This corresponds to the signal line Z3ttl'l14 in the figure.
信号線１５お工び１６がハイ・レベルとなったとき論理
積回路Ｇ１の出力線１７はハイ・レベルとなり論理積回
路Ｇ２に伝達される。信号線１８は第１図における信号
線１１またはｌｚに対応する。信号線１７および１８が
ハイ・レベルとなったときは論理積回路Ｇ２の出力線１
９がハイ・レベルとなりバス上にパリティ・エラーが検
出される。When the signal lines 15 and 16 go high, the output line 17 of the AND circuit G1 goes high and is transmitted to the AND circuit G2. Signal line 18 corresponds to signal line 11 or lz in FIG. When signal lines 17 and 18 are at high level, output line 1 of AND circuit G2
9 goes high and a parity error is detected on the bus.
これによりバス・ゲート回路であるＢＵＳ−ＧＴが共通
バスＢ１とＢ２の接続を断とする。As a result, the bus gate circuit BUS-GT disconnects the common buses B1 and B2.
例として第１図において制御盤ＣＯＮ’ｌ’ Ｉが運用
状態のときに共通バス１３Ｕｓ−Ａに接続された送受信
盤ＴＲＩが障害を発生し、たときには第１の共通バスＢ
ＵＳ−１と共通バスＢＵＳ−Ａの接続が切替盤５Ｗ−Ｉ
Ａによって断とされるので、共通バスＢＵＳ−Ａに接続
した送受信盤Ｔ Ｒ，ｌ〜Ｔ Ｒｎは制御盤Ｃ０ＮＴ１
から制御できなくなるので、第１の共通バスＢ ’Ｕ
Ｓ −１は共通バスＢＵＳ−Ａの影ζｕ：、５を受けず
、制御盤Ｃ０ＮＴ １は共通バスＢＵＳ−Ｈに接続され
た送受信盤ＴＲＩ〜ＴＲｎを制御できる。For example, in FIG. 1, when the control panel CON'l' I is in operation, the transmitter/receiver panel TRI connected to the common bus 13Us-A has a fault, and if the first common bus B
Connection between US-1 and common bus BUS-A is via switch board 5W-I
Since the transmitter/receiver boards T R, l to T Rn connected to the common bus BUS-A are disconnected by the control board C0NT1.
Since it becomes uncontrollable from the first common bus B'U
S-1 is not affected by the common bus BUS-A, and the control panel C0NT1 can control the transceiver panels TRI to TRn connected to the common bus BUS-H.
以上の説明により明らかなように、本発明によれば送受
信盤が直接接続されるバスを２系統に分割し、各々の系
と制御盤との接続を接・断できるように構成することに
エリ、１台の送受信盤の障害だけでに制御装置の機能が
完全に停止することはなく、従来に比較し、システムの
信頼性が数段向上するという効果がある。As is clear from the above explanation, according to the present invention, the bus to which the transmitter/receiver board is directly connected is divided into two systems, and the configuration is such that the connection between each system and the control board can be connected/disconnected. The function of the control device does not completely stop due to a failure in one transceiver panel, and the system has the effect of improving system reliability by several steps compared to the conventional system.
第１図は本発明によるバス切替制御方式の実施例を示す
ブロック図、第２図は切替盤の詳細を示すブロック図で
ある。
ＯＰ・・・操作盤
ＣＯＮ’ｌｌ’１ 、Ｃ０ＮＴ２・・・制御盤５Ｗ−Ｉ
Ａ、−２Ａ、−ＩＢ、−２Ｂ・・・切替盤Ｔ Ｉ（、ｌ
〜Ｔ Ｒｎ・・・送受信盤Ｔ・・・終端盤
ＢＵＳ−ＧＴ・・バス・ゲート回路
ＰＤ・・・パリティ検出回路
Ｇｌ 、Ｇ２・・・ゲート回路
特許出願人 日本屯気株式会社
代理人 弁理士 井 ） ロ 壽FIG. 1 is a block diagram showing an embodiment of the bus switching control system according to the present invention, and FIG. 2 is a block diagram showing details of the switching board. OP...Operation panel CON'll'1, C0NT2...Control panel 5W-I
A, -2A, -IB, -2B...Switching board T I (, l
~T Rn... Transmitter/receiver board T... Terminal board BUS-GT... Bus gate circuit PD... Parity detection circuit Gl, G2... Gate circuit Patent applicant Nippon Tunki Co., Ltd. Agent Patent attorney I) Ro Hisashi
Claims (1)
複数の送受信盤を制御する制御盤と、共通バスの接・断
を行うための複数の切替盤と、パリティ・エラーを検出
するためのパリティ検出部とを含み、前記制御盤に接続
される共通バスは２系統に分割してそれぞれの系の共通
バスに前記切替盤を接続し、さらに前記各切替盤に接続
される共通バスにそれぞれ前記複数の送受信盤を接続し
、切替盤を接にすることにより、一方の系の共通バスに
よって前記制御盤と複数の送受信盤を接続し、複数の送
受信盤のうち１以上に障害が発生した場合、前記パリテ
ィ検出部によって前記切替盤を断とすることによって複
数の送受信盤を前記一方の系の共通バスよシ切離し、他
方の系の共通バスによって前記制御盤と複数の送受信盤
を接続するように構成したことを特徴とするバス切替制
御方式。A plurality of transmitter/receiver panels for transmitting and receiving data, a control panel for controlling the plurality of transmitter/receiver panels, a plurality of switching panels for connecting/disconnecting the common bus, and a controller for detecting parity errors. The common bus connected to the control panel is divided into two systems, and the switching panel is connected to the common bus of each system, and the common bus connected to each switching panel is further connected to the common bus of each system. By connecting the plurality of transmitting/receiving panels and bringing the switching panels into contact, the control panel and the plurality of transmitting/receiving panels are connected by a common bus of one system, and a failure occurs in one or more of the plurality of transmitting/receiving panels. In this case, the plurality of transmitting/receiving boards are disconnected from the common bus of the one system by disconnecting the switching board by the parity detection unit, and the control board and the plurality of transmitting/receiving boards are connected by the common bus of the other system. A bus switching control system characterized by being configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58075470A JPS59201548A (en) | 1983-04-28 | 1983-04-28 | Bus changeover control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58075470A JPS59201548A (en) | 1983-04-28 | 1983-04-28 | Bus changeover control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59201548A true JPS59201548A (en) | 1984-11-15 |
Family
ID=13577225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58075470A Pending JPS59201548A (en) | 1983-04-28 | 1983-04-28 | Bus changeover control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59201548A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5037115A (en) * | 1973-08-08 | 1975-04-07 | ||
| JPS55957A (en) * | 1978-06-19 | 1980-01-07 | Nec Corp | Information processing system |
-
1983
- 1983-04-28 JP JP58075470A patent/JPS59201548A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5037115A (en) * | 1973-08-08 | 1975-04-07 | ||
| JPS55957A (en) * | 1978-06-19 | 1980-01-07 | Nec Corp | Information processing system |
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