JPS5920165U

JPS5920165U - Peak detection circuit

Info

Publication number: JPS5920165U
Application number: JP11413082U
Authority: JP
Inventors: 荒船　泰成
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1982-07-29
Filing date: 1982-07-29
Publication date: 1984-02-07
Also published as: JPH0240541Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図、第２図及び第３図は従来のピーク検波回路の回
路図、第４図は第３図の各部の波形を示す波形図、第５
図は本考案になるピーク検波回路の一実施例を示す回路
図、第６図は第５図の各部の波形を水子波形図、第７図
は第５図のピーク検波回路をＡＣＣ回路に適用した一実
施例を示すブロック図である。− 図中符号、１７は第１の差動増幅器、１８゜１９は第１
、鯖２の電流分流回路、２０．２１は第２、第３の差動
増幅器、２２は積分回路、Ｑ０〜ＱＩＯはトランジスタ
、Ｒ１−Ｒ１は第１〜第４の電流に係わる抵抗である。Figures 1, 2, and 3 are circuit diagrams of conventional peak detection circuits, Figure 4 is a waveform diagram showing the waveforms of each part in Figure 3, and Figure 5
The figure is a circuit diagram showing one embodiment of the peak detection circuit of the present invention, Figure 6 is a water waveform diagram of the waveforms of each part of Figure 5, and Figure 7 is an ACC circuit of the peak detection circuit of Figure 5. FIG. 2 is a block diagram showing an applied example. - In the figure, 17 is the first differential amplifier, 18°19 is the first
, the current shunting circuit of Saba 2, 20.21 are second and third differential amplifiers, 22 is an integrating circuit, Q0 to QIO are transistors, and R1 to R1 are resistors related to the first to fourth currents.

Claims

[Scope of utility model registration request]

a first differential amplifier comprising first and second transistors into which a signal is input; and a third and second differential amplifier provided to divide the collector current of the first transistor into a first current and a second current. a first current shunting circuit made up of four transistors; and a second current made up of fifth and sixth transistors provided to shunt the collector current of the second transistor into a third current and a fourth current. A shunt circuit and a first circuit having an equal value provided in each of the first and fourth current flow paths.
and a fourth resistor, second and third resistors provided in the second and third current flow paths and having the same value and different values from the first and fourth resistors, and one of the signal a second differential amplifier comprising seventh and eighth transistors, the bases of which are connected to respective collectors of the third and fifth transistors associated with the first and third currents, in order to detect the peak of the current; and a tenth and ninth transistor whose bases are connected to respective collectors of the fourth and sixth transistors associated with the second and fourth currents in order to detect the other peak of the signal. 3 differential amplifiers, and is connected between the collector outputs of the seventh and ninth transistors or the eighth and tenth transistors of the second and third differential amplifiers having equal common emitter currents and the power supply. A peak detection circuit characterized in that it is configured to obtain a detection output using an integrating circuit.