JPS59203209A - Digital signal detector - Google Patents

Digital signal detector

Info

Publication number
JPS59203209A
JPS59203209A JP58077017A JP7701783A JPS59203209A JP S59203209 A JPS59203209 A JP S59203209A JP 58077017 A JP58077017 A JP 58077017A JP 7701783 A JP7701783 A JP 7701783A JP S59203209 A JPS59203209 A JP S59203209A
Authority
JP
Japan
Prior art keywords
pattern
digital
circuit
signal
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58077017A
Other languages
Japanese (ja)
Inventor
Kaoru Iwakuni
薫 岩國
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58077017A priority Critical patent/JPS59203209A/en
Publication of JPS59203209A publication Critical patent/JPS59203209A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10527Audio or video recording; Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To digitize the detection processing and make adjustment unnecessary and to enhance the degree of tolerance to noise by collating a digital pattern, to which the waveform of a reproduced signal is converted in an A/D converting circuit, with a standard pattern to detect the signal. CONSTITUTION:The waveform of the reproduced signal which is applied to the input of an analog-digital converting circuit 4 is converted differentially to a binary digital signal by a delay device 8 and a comparator 7. This digital signal is converted to parallel data by a series-parallel converter 9 to obtain a digital pattern P corresponding to the input signal. This digital pattern P is sent to a pattern collating circuit 5 and is compared and collated with standard patterns Qj. They are compared with each other in the collating circuit 5, and a code Mi corresponding to a standard pattern is outputted as the detection result. Differential conversion is used in the analog-digital converting circuit to enhance the degree of tolerance to noise having low frequency components, and standard patterns are selected to cope flexibly with the influence of peak shift and the variance of characteristics of a recording medium.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ディジタル・テープレコーダ、ディジタル・
ディスク等のディジタル信号の磁気及び光学式記録再生
システムにおけるディジタル信号従来例の構成とその問
題点 近年、ディジタル・オーディオ、オフィスオートメーシ
ョン等の発展は目ざましいものがあるが、これらのディ
ジタル・データの記録再生システムの中で、ディジタル
信号検出装置は重要な位置を占めるものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to digital tape recorders, digital
Conventional configurations of digital signals in magnetic and optical recording and reproducing systems for digital signals such as disks, and their problems In recent years, there has been remarkable development in digital audio, office automation, etc., but the recording and reproducing of these digital data is In the system, a digital signal detection device occupies an important position.

以下に従来のディジタル信号検出装置について説明する
。第1図は従来のディンタル信号検出装置の構成図であ
り、1は等化回路、2は比較器、3は復調回路である。
A conventional digital signal detection device will be explained below. FIG. 1 is a block diagram of a conventional digital signal detection device, in which 1 is an equalization circuit, 2 is a comparator, and 3 is a demodulation circuit.

このように構成された従来のディジタル信号検出装置の
動作を以下に説明する。まず第2図(a)に示すような
再生信号波形を等化回路1の入力に加えた場合を考える
と、再生信号波形Id等化回路1によって波形等化され
、ピークシフトの影響が除去され、第2図(b)に示す
様な記録時の波形に近い形にもどされて比較器2に加え
られる。この比較器2では比較電圧Vvef  と比較
することで波形整形を行い、第2図(C)で示すような
信号が復調回って復調を行い、出力には検出結果の符号
が現われることになる。
The operation of the conventional digital signal detection device configured as described above will be explained below. First, consider the case where a reproduced signal waveform as shown in FIG. 2(a) is applied to the input of the equalization circuit 1. The reproduced signal waveform Id is equalized by the equalization circuit 1, and the influence of peak shift is removed. , is restored to a waveform similar to that at the time of recording, as shown in FIG. 2(b), and is applied to the comparator 2. This comparator 2 performs waveform shaping by comparing with the comparison voltage Vvef, and demodulates a signal as shown in FIG. 2(C), and the sign of the detection result appears in the output.

しかしながら、上記の従来の構成では等化回路1及び比
較器2がアナログ回路によって構成されているため、倣
妙な調整を必要とし、信号対雑音比の劣化と雑音による
誤動作の恐れがあり、さらには高集積度のIC化が困難
であるうえに記録媒体の特性の違い等に対して適応性に
乏しいという問題点を有していた。
However, in the conventional configuration described above, the equalizer circuit 1 and the comparator 2 are configured with analog circuits, which requires delicate adjustment, which may cause deterioration of the signal-to-noise ratio and malfunction due to noise. However, it is difficult to fabricate a highly integrated IC, and it also has problems in that it is not adaptable to differences in the characteristics of recording media.

発明の目的 本発明は上記従来の問題点を解消するもので、装置の大
部分をディジタル回路で構成することにより、調整が不
要で雑音による誤動作の恐れも極めて小さく、容易にI
C化を行うことができ、さらにパターン照合の手法の導
入により柔軟な適応性を有するディジタル信号検出装置
を提供することを目的とする。
Purpose of the Invention The present invention solves the above-mentioned conventional problems. By configuring most of the device with digital circuits, there is no need for adjustment, the risk of malfunction due to noise is extremely small, and the I/O can be easily installed.
It is an object of the present invention to provide a digital signal detection device that can perform C conversion and also has flexible adaptability by introducing a pattern matching method.

発明の構成 本発明は、入力された再生信号波形をディジタル・パタ
ーンに変換するアナログディジタル変換回路と、変調量
に基づいた標準パターンを格納する標準パターン記憶回
路と、入力された再生信号よす得うれたディジタル・パ
ターンと標準パターンとを比較・照合し、最も入カバタ
ーンに近い標準パターンに対応する符号を出力するパタ
ーン照合回路とを備えたディジタル信号検出装置であり
、動作の安定性と柔軟性を併せ持つものであるO実施例
の説明 第3図は本発明の一実施例におけるディジタル信号検出
装置の構成を示すものであって、4はアナログディジタ
ル変換回路、5はパターン照合回路、6は標準パターン
記憶回路である。
Structure of the Invention The present invention includes an analog-to-digital conversion circuit that converts an input reproduction signal waveform into a digital pattern, a standard pattern storage circuit that stores a standard pattern based on the amount of modulation, and a digital pattern that converts an input reproduction signal waveform into a digital pattern. This is a digital signal detection device equipped with a pattern matching circuit that compares and matches the obtained digital pattern with a standard pattern and outputs the code corresponding to the standard pattern closest to the input pattern, and has stable and flexible operation. Description of Embodiment FIG. 3 shows the configuration of a digital signal detection device in an embodiment of the present invention, in which 4 is an analog-to-digital conversion circuit, 5 is a pattern matching circuit, and 6 is a standard It is a pattern memory circuit.

第4図はアナログディジタル変換回路4の一構成例を示
したもので、γは比較器、8は1標本化時間の遅延器、
9は直並列変換器である。
FIG. 4 shows an example of the configuration of the analog-to-digital conversion circuit 4, where γ is a comparator, 8 is a delay device with one sampling time,
9 is a serial/parallel converter.

以下その動作を説明する。The operation will be explained below.

まず、アナログディジタル変換回路4の入力に加えられ
た再生信号波形は遅延器8と比較器7により2値のディ
ジタル信号に差分変換される。この操作はいわゆるデル
タモジュンーショント同等のものである。このディジタ
ル信号は直並列変換器9によって並列データに変換され
入力信号に対応したディジタル・パターンPが得られる
。次に、このディジタル・パターンPはパターン照合回
路5に送られ標準パターン照合 と比較・照合される。
First, the reproduced signal waveform applied to the input of the analog-to-digital conversion circuit 4 is differentially converted into a binary digital signal by the delay device 8 and the comparator 7. This operation is equivalent to the so-called delta modulation. This digital signal is converted into parallel data by a serial/parallel converter 9 to obtain a digital pattern P corresponding to the input signal. Next, this digital pattern P is sent to the pattern matching circuit 5 and compared and matched with a standard pattern matching.

この標準パターンは第5図に示すように、まず既知の符
号Mj を変調器及び記録再生糸11を通すことにより
Mj に対する再生信号波形を作り、それを該アナログ
ディジタル変換回路4に加えて得られたディジタル・パ
ターンを平均したものを符号Mj に対応する標準パタ
ーンq+  とするという方法で決定され、標準パター
ン記憶回路6に格納されている。パターン照合回路5で
は入力再生波形に対応したディンタル・パターンP、!
Ji亭パターンQ〕を比較し距離Dフ を次式により算
出する。
This standard pattern, as shown in FIG. The standard pattern q+ corresponding to the code Mj is determined by averaging the digital patterns obtained, and is stored in the standard pattern storage circuit 6. The pattern matching circuit 5 generates a digital pattern P, ! corresponding to the input reproduced waveform.
Ji-tei pattern Q] is compared, and the distance D is calculated using the following formula.

Dj=lP−Qコ 12 この距離Dコ を全ての標準パターンQj について計
算し、その中で最小値D1を与える標準パターンQiに
対応する符号M1を求める0以上のようにして検出符号
出力に検出結果として符号Miが出力さnる。
Dj = lP - Q 12 Calculate this distance D for all standard patterns Qj, and find the code M1 corresponding to the standard pattern Qi that gives the minimum value D1. As a result, the code Mi is output.

このように本実施例によれば、アナログディジタル変換
回路に差分変換を使用したことにより周波数成分の低い
雑音に対する余裕度を高くすることができ、IC化も容
易であり、さらに標準パターンを選択することによって
ピーク・シフトの影響及び記録媒体の特性の変化に柔軟
に対応することができる。
In this way, according to this embodiment, by using differential conversion in the analog-to-digital conversion circuit, it is possible to increase the margin against noise with low frequency components, it is easy to integrate it into an IC, and it is also possible to select a standard pattern. This makes it possible to flexibly respond to the effects of peak shifts and changes in the characteristics of the recording medium.

なお、本実施例ではアナログディジタル変換回路4に差
分変換を用いたが、4bitないし5bit程度のA/
D変換器を用いてもよく、ウオルシュ・アダマール変換
器を付加してもよい。この場合は装置の規模は犬となる
が、各パターンのピント数を少くしても同等の検出能力
が得られる。またノくターン照合回路5で距離尺度とし
てユークリッド距離を用いだが、マノーラノビス距離等
を用いてもよく、さらにDPマツチング法による時間軸
の正規化の処理を付加してもよい0この場合はピーク・
シフト及び再生信号波形の時間軸変動に対する余裕度を
大幅に向上させることができる。
In this embodiment, differential conversion is used in the analog-to-digital conversion circuit 4.
A D converter may be used, or a Walsh-Hadamard converter may be added. In this case, the scale of the device will be smaller, but the same detection ability can be obtained even if the number of focuses for each pattern is reduced. In addition, although Euclidean distance is used as a distance measure in the turn matching circuit 5, Manola Nobis distance or the like may also be used, and time axis normalization processing using the DP matching method may be added.
It is possible to significantly improve the margin against time axis fluctuations of the shift and reproduced signal waveforms.

発明の効果 本発明は、信号の検出をアナログディジタル変換回路に
より再生信号波形から変換されたディジタル・パターン
と標準パターンとのパターン照合によって行うことによ
り、検出のだめの処理を大幅にディジタル化することが
でき、調整の必要がなく、雑音に対する余裕度も高く、
記録媒体等の変化に対する適応性もあり、さらにIC化
も容易であるという優れたディジタル信号検出装置を実
現できるものである。
Effects of the Invention The present invention detects signals by matching a standard pattern with a digital pattern converted from a reproduced signal waveform by an analog-to-digital conversion circuit, thereby significantly digitizing the detection process. There is no need for adjustment, and there is a high margin against noise.
It is possible to realize an excellent digital signal detection device that is adaptable to changes in recording media, etc., and can be easily integrated into an IC.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のディジタル信号検出装置の構成図、第2
図(2L)〜(C)は第1図の要部の波形図、第3図は
本発明の一実施例におけるディジタル信号検出装置の構
成図、第4図は第3図におけるアナログディンタル変換
回路の詳細図、第5図は第3図における標準パターンQ
j の決定法を示す構成図である。 1 ・・等化回路、2 ・・・比較器、3・・・・・・
復調回路、4・・・・・アナログディジタル変換回路、
5・・・・・パターン照合回路、6・・・・・標準パタ
ーン記憶回路、7・・・・・比較器、8・・・・・遅延
器、9・・・・直並列変換器。
Figure 1 is a configuration diagram of a conventional digital signal detection device;
Figures (2L) to (C) are waveform diagrams of the main parts of Figure 1, Figure 3 is a configuration diagram of a digital signal detection device in an embodiment of the present invention, and Figure 4 is an analog-to-digital conversion diagram in Figure 3. Detailed diagram of the circuit, Figure 5 is the standard pattern Q in Figure 3.
FIG. 2 is a configuration diagram showing a method for determining j. 1... Equalization circuit, 2... Comparator, 3...
demodulation circuit, 4...analog-digital conversion circuit,
5...Pattern matching circuit, 6...Standard pattern storage circuit, 7...Comparator, 8...Delay device, 9...Serial to parallel converter.

Claims (1)

【特許請求の範囲】[Claims] 再生信号波形を入力とし、その入力に対応したディンタ
ル・パターンを出力とするアナログディジタル変換回路
と、変調前に基づいた標準パターンを格納する標準パタ
ーン記憶回路と、前記アナログディジタル変換回路の出
力と標準パターンとを照合するパターン照合回路とより
なり、入力された再生信号波形に対応するディジタル・
パターンに最も類似した標準パターンを求め、その標準
パターンに対応する符号語を検出信号として出力するこ
とを特徴とするディンタル信号検出装置。
an analog-to-digital conversion circuit that receives a reproduced signal waveform as an input and outputs a digital pattern corresponding to the input; a standard pattern storage circuit that stores a standard pattern based on before modulation; It consists of a pattern matching circuit that matches the pattern, and a digital signal corresponding to the input playback signal waveform.
A digital signal detection device characterized by finding a standard pattern that is most similar to a pattern, and outputting a code word corresponding to the standard pattern as a detection signal.
JP58077017A 1983-04-30 1983-04-30 Digital signal detector Pending JPS59203209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58077017A JPS59203209A (en) 1983-04-30 1983-04-30 Digital signal detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58077017A JPS59203209A (en) 1983-04-30 1983-04-30 Digital signal detector

Publications (1)

Publication Number Publication Date
JPS59203209A true JPS59203209A (en) 1984-11-17

Family

ID=13621983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58077017A Pending JPS59203209A (en) 1983-04-30 1983-04-30 Digital signal detector

Country Status (1)

Country Link
JP (1) JPS59203209A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05217289A (en) * 1990-06-29 1993-08-27 Digital Equip Internatl Gmbh Method and apparatus for analog-to-digital signal conversion
WO2001061700A1 (en) * 2000-02-17 2001-08-23 Hitachi, Ltd Information reproducing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05217289A (en) * 1990-06-29 1993-08-27 Digital Equip Internatl Gmbh Method and apparatus for analog-to-digital signal conversion
WO2001061700A1 (en) * 2000-02-17 2001-08-23 Hitachi, Ltd Information reproducing device

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