JPS59211385A - Smear correcting circuit - Google Patents

Abstract

PURPOSE:To improve the S/N ratio for a smear correcting circuit by writing a smear signal in response to a level of a smear signal detected on a prescribed line and a storage capacity of an output register section into a memory. CONSTITUTION:A peak value (n) is detected by a peak detecting means 18 from a smear signal for one line's share from an A/D converter 12. The peak value (n) is applied to a level comparison means 19, where the value is compared with a reference level from an ROM20. This detected output is applied to an operating means 21 to decide a line number N of the smear signal to be added and stored in the output register section 4 and a line number M of the smear signal to be added and stored in a memory 6.

Description

[Detailed description of the invention] Industrial applications The present invention relates to improvements in smear correction circuits.

BACKGROUND TECHNOLOGY AND ITS PROBLEMS First, the smear that occurs in a CCD@ solid-state imaging device will be explained with reference to FIGS. 1 and 2. In FIG. ) shows a solid-state imaging device consisting of a CCD as a whole, for example in the case of a frame transfer type, which includes a photo sensor section (2), a storage section (3).
and an output register section (4). In addition, the steel wire parts, namely the storage part (3) and the output register part (4)
) are shielded from light. Light from a subject passes through a lens system and enters the surface of the photosensor section (2). By doing so, an image of charges corresponding to the incident light is formed on the photosensor section (2). During one field period, that is, one second, the charge image on the photosensor section (2) is transferred to the storage section (
3). Further, the charge image in the storage section (3) is transferred to the output 1/register section (4), where it is converted into an inner column signal and taken out as an imaging output.

As shown in FIG. 1, consider a case where a relatively bright light portion enters a portion of the photosensor section (2) and a charge image is formed there. In this way, when the charge is transferred from the photo sensor section (2) to the storage section (3), the charges in each part of the photo sensor section (2) pass through the incident part of this light and are excited by this light. Since electrons are generated, when this imaging output is reproduced by a negative i-ray tube of a television receiver, a bright image I corresponding to the portion of the incident light in Figure 1 is projected as shown in Figure 2. At the same time, a bright band-like image q in the vertical direction having 6 of the image I is formed. The brightness of this image q is lower than that of image (2).

The charge image on the solid-state imaging device (20) corresponding to the image q is generally called a smear.

Therefore, conventionally, a smear correction circuit as shown in FIG. 3IC has been used to prevent the occurrence of smear. This smear correction circuit will be explained below. (1) is a solid-state imaging device similar to that shown in FIG.

A light shielding part (2a) is provided, for example, in the last row at the bottom end (the top end is also possible) of the photosensor part (1). Then, the imaging output from the output register (4) is supplied to the movable contact a of the changeover switch (electronic switch is possible) (5).

One fixed contact of the changeover switch (5) is connected to the input side of the 1-line memory (6). The output side of the memory (6) is connected to its input side via an on-off switch (7). (8) is a differential amplifier as a subtracter, the other fixed liquid AC of the changeover switch (5) is connected to its non-inverting input terminal, and the output side of the memory (6) is connected to its inverting input terminal. be done. (9) is an output terminal to which the output of the differential amplifier (8) is supplied.

Next, the operation of the smear correction circuit shown in FIG. 3 will be explained. An imaging signal from an output register section (4) of a solid-state imaging device (1) is supplied to a non-inverting input terminal of a differential amplifier (8) via a changeover switch (5). This imaging signal includes a smear component. Light shielding part (2a) of photosensor part (2)
When the signal of the part is output from the output register section (4), the movable contact a of the changeover switch (5) is switched to the fixed contact A, and the smear signal of one line with the vertical retrace period is stored in the memory ( 6).

Also, at this time, the on/off switch (7) is turned on for approximately one field period, so the smear signal Sm is approximately 1 field.
It is held in the field period memory (6). The movable contact a of the changeover switch (5) is connected to the above-mentioned light shielding part (2a).
) is switched to the fixed contact C side except for one line period when the smear signal is supplied, so the smear signal is subtracted from the imaging signal containing the smear component in the differential amplifier (8), and the output terminal At (9), the image signal from which the smear component has been removed is output.

By the way, in the conventional smear correction circuit shown in FIG.
Since noise is mixed in the smear signal taken out from the line memory (6), the noise is mixed in the image signal finally obtained from the output terminal (9), and instead of correcting the smear, the image signal The S/N of the signal deteriorates.

Therefore, in order to reduce the 8/N deterioration of the smear-corrected imaging signal, in the improved conventional smear correction circuit, the light shielding part (2a) of the photosensor part (2) of the solid-state imaging device (1) is NH (where N is a natural number and ■ (is the horizontal period), select this N as large as possible, and add the smear signal for NH during the vertical retrace period in the 1-line memory (6). The level of the added smear signal was read out from the memory (6).This method improves smear-corrected imaging, but it is still insufficient.

Therefore, in the conventional smear correction circuit that has been further improved, reading of the smear signal from the output register section (4) of the solid-state imaging device (1) is stopped only during the MH period (where M is a natural number) during the vertical retrace period. Then, this M is selected as large as possible, and then a smear signal with a level four times the level of one line is read out from the output register section (4), and this is stored in the one line memory (6). , and was attenuated and supplied to the puller (8). In this way, the noise level is further improved as shown in FIG. 3.

However, in such a smear correction circuit, there is a natural limit to the signal storage capacity of the output register section (4).
M cannot be selected too large. That is, if M is made too large, an overflow will occur in the output register section (4). Therefore, even with such a conventional smear correction circuit, it is difficult to obtain an imaging signal with a sufficiently good S/N ratio.

OBJECTS OF THE INVENTION In view of the above points, the present invention proposes a smear correction circuit that further improves the S/H compared to the prior art.

Summary of the Invention The present invention has a memory that stores a smear signal obtained from a solid-state imaging device, and converts the smear signal read from the memory into a smear signal obtained from the solid-state imaging device using a predetermined synthesis ratio. In a smear correction circuit that removes smear components from an image signal by combining it with an image signal containing the smear component, Level detecting means for detecting, and control for adding and accumulating smear signals for a predetermined number of lines in the output register section according to the level of the detected smear signal and the storage capacity of the output register section, and then reading and writing them into the memory. means.

According to the present invention, it is possible to obtain a smear correction circuit in which the S/N ratio is further improved compared to the conventional one.

Example One embodiment of the invention will now be described with reference to FIG.

Incidentally, in FIG. 4, parts corresponding to those in FIG. 3 described above are given the same symbols, and some redundant explanations will be omitted. (11 is a 1;q1 body imaging device consisting of a CCD similar to that shown in FIG. 3, and is also a frame transfer type. The output from the output register section (4) of the solid-state imaging device H (11) is as follows. After being supplied to the A/DF converter circle via the amplifier αD and digitized, it is supplied to the synthesizer (digital synthesizer) (8). (9) is the synthesized output from the synthesizer (8). In addition, the output of the synthesizer (8) is sent to the 1-line memory (6) through the fixed contact A and the movable contact A of the changeover switch (IJ (having a movable contact a and fixed contacts A and C)). The output read from the memory (6) is sent to a digital attenuator (14) for determining the synthesis ratio. via the synthesizer (8) and subtracted from the output from the A/D converter circle.

Attenuator [4] (7) Let the damping ratio be a surface. However, N and M are each natural numbers. Incidentally, this attenuator (14) may be provided on the long sword side of the 12-in memory (6). Also, memory (6
) is read out through the fixed contact C and movable contact a of the changeover switch Q31. J f61 K
It is designed to be supplied and kept in circulation.

05) is a clock generator that supplies a transfer lock signal to the solid-state imaging device (1).

(161 indicates a functional block of the microprocessor.

``a'' is a control means, and the above-mentioned memory (6), changeover switch (13+) and clock generator a9 are controlled by this control means α.aQ is a peak detection means, The output is supplied to this, its peak value is detected, and supplied to the level comparison means a9, where it is compared with the reference level from the ROM (a).The comparison output is supplied to the calculation means C!υ, and its peak value is detected. The output of the calculation result is supplied to the control means QD.

Next, the detailed configuration and operation of the smear correction circuit shown in FIG. 4 will be explained with reference to the flowchart shown in FIG. For example, the light shielding portion (2a) at the lower end of the photosensor portion (2) of the solid-state imaging device (1) corresponds to 19H of the vertical retrace period. First, the smear signal of the first line in the vertical retrace period is vertically transferred from the storage section (3) to the output register section (4) by the vertical transfer lock from the clock generator block 9. . Then, due to the horizontal transfer lock from the clock generator a9, the smear signal of the first line of the vertical retrace period written in the output register section (4) is read out and the anchor multiplier aD
The signal is supplied to the A/D converter a2 via the A/D converter a2. The digitized smear signal for one line obtained from the A/D conversion converter is supplied to the peak detection means +I81, and its peak value n is detected. The peak value n of this smear signal is supplied to the level comparison means α9 and compared with a reference level from "[ROM (20+)".
It consists of ~16 unit levels. Therefore, in this case, the storage capacity of the output register section (4) is equal to or higher than the 17 unit level. Then, in the level comparison means, the peak value n of the smear signal detected by the peak value detection means θ barrel is determined.
It is detected which level of the above-mentioned reference level corresponds to. Then, by supplying this detection output to the calculation means (21), the number N of lines of the smear signal to be added and accumulated in the output register section (4) and the number of lines of the smear signal to be added and accumulated in the memory (6) are set to 4. is determined. In the calculation means (21) of this embodiment, as shown in the following table, NxM is set to a constant value, for example 16, and when the peak value n is 1. When the unit level is N, N is 1, and the peak l'Iin is 2. And for the 3 unit level, N is 2, and the peak value n is 4 to 7 units level N.
is set to 16, and the control means 07
) and also simplifies the configuration of the attenuator I.

<Table> Once the values of N and M are determined in this way, first, the vertical transfer lock from the clock generator a9 is supplied to the storage section (3) of the solid-state imaging device [11], and the N247 portion of the vertical retrace period is Smear signal output register section (4
). In this case, reading of signals from the output register section (4) is stopped during the N line period. After that, N2 added and accumulated in the output register section (4)
Read out the smear signal for 47 minutes and use the amplifier (11) -
The signal is supplied to the synthesizer (8) via the AD converter t1z. Then, this smear signal of N247 after passing through the synthesizer (8) is written and stored in the memory (6) through the fixed contact 0 and the movable contact a of the changeover switch 0.

When the peak value n of the smear signal is smaller than 16, the above-mentioned output register section (4) is reset, 8247th part of the child signal is added and accumulated again, and the readout output is sent to the above-mentioned amplifier a1J-4. Converter circle-synthesizer (8)-
Addition and accumulation are made to the memo 6 (6) via the changeover switch αJ. Perform this operation with M(=-H)
Repeat several times. Thereafter, the movable contact a of the changeover switch a3 is switched to the fixed contact C to form a closed loop including the memory (6), and the contents of the memory (6) are circulated during a period excluding the vertical retrace period of one field. When the detection of smear signals for 16 lines is completed during the vertical retrace period, the photo sensor section (2) of the image pickup signal
Transfer and storage from the barge section (3) to the storage section (3), transfer from the barge section (3) to the output register section (4), and read out from the output register section (4). is supplied to the A/D converter (12) via the amplifier 01), and the obtained digitized image signal is supplied to the synthesizer (8). The smear signal for MN lines is supplied to the attenuator I, attenuated to KqD+, and then supplied to the stage generator (8) and subtracted from the imaging signal. An imaging signal from which components have been removed is obtained.

Then, when the next 7-yield vertical blanking period arrives, the contents of the memory (6) are reset and the above-described operation is repeated again. Note that the detection of this smear component may be performed for each field as described above, or may be performed for each plurality of fields.

S/N is greatly improved. In other words, when the level (peak value) of the smear signal for 12 inches is small, the S/N is greatly improved by addition accumulation (synchronous addition) in the output register section, and the level (peak value) of the smear signal for one line is increased.
When is large, by using the addition and accumulation of the 1-line memory in addition to the addition and accumulation of the output register section,
An imaging signal with as good an S/N ratio as possible can be obtained depending on the level of the smear signal and the storage capacity of the output register section.

In the above embodiments, a frame transfer type solid-state imaging device has been described, but it can also be applied to an interline transfer type solid-state imaging device. Also, BBD
Other CTDs can also be used, such as.

Effects of the Invention According to the present invention described above, it is possible to obtain a smear correction circuit in which the S/N ratio is further improved compared to the conventional one.

[Brief explanation of the drawing]

Fig. 1 is a route diagram showing a solid-state imaging device to explain the smear phenomenon, Fig. 2 is a pattern diagram showing a TV screen when a smear phenomenon occurs, and Fig. 3 is a block diagram showing a conventional smear correction circuit. 4 is a block diagram showing an embodiment of the smear correction circuit according to the present invention, and FIG. 5 is a flowchart for explaining the same. (11 is a solid-state imaging device, (2) is a photosensor section, (3 is
) bus storage section, +41 is the output register section, o (to)
is a level detection means, and aη is a control means.

Claims (1)

[Claims] It has a memory that stores a smear signal obtained from the solid-state imaging device, and converts the smear signal read from the memory into an imaging signal containing a smear component obtained from the solid-state imaging device with a predetermined synthesis ratio. A level for detecting the level of the smear signal of a predetermined line read from the output register section of the solid-state imaging device in the smear correction circuit that removes the smear component in the imaging signal by combining with a detection means, and a control means for adding and accumulating smear signals for a predetermined number of lines in the output register section according to the level of the detected smear signal and the storage capacity of the output register section, and then reading the smear signals and writing them into the memory. A smear correction circuit having the following characteristics.