JPS5925280A - Optical input MOS transistor - Google Patents

Abstract

PURPOSE:To obtain a small one chip photo input MOS transistor by a method wherein a gate electrode is composed of a solar battery structural part and a metallic layer immediately thereunder. CONSTITUTION:The gate electrode 14 of a photo input MOS transistor is composed by providing the metallic layer 14c immediately under superposition layers 14a and 14b which form the solar battery structure. In case of no photo input, a solar battery gate part (circles in chain lines) becomes a condenser and a diode, and then the MOS transistor becomes in the state of input ''0''. In case of photo input, an electromotive force generates at the solar battery gate part (circles in chain lines), and a voltage is impressed on the gate, therefore the MOS transistor becomes in the state of input ''1''. Thus, the photo power of the solar battery is impressed on the gate oxide film via the layer 14c, and accordingly the threshold voltage can be reduced. Therefore, a multi-layer structure can be realized without necessitating a solar battery exclusive area, and then a small one chip photo input MOS transistor can be realized.

Description

[Detailed description of the invention] The present invention relates to an optical input MO3) transistor.

By converting the human input signal of a MOS (MOS) transistor into light, the following transistor can be realized.

■ A power MOS transistor that uses a F1 coupler to achieve almost complete insulation between the input and output systems.

■ MOS transistors that can be manually operated directly from optical communications.

Such a nine-power MO3I transistor, for example,
As shown in the figure, this can be realized by using a solar cell structure for the solar cell 41. Of course, when the p-type silicon substrate 1 has n-swelled diffusion layers 2a and 2b and the insulating oxide film 3 is formed on the substrate 1, the gate electrode 4 is
Shape, 1! The solar cell structure is composed of a phosphor layer 4a and an n-type phosphor layer 4b superimposed thereon.

In the figure, 5a is a source electrode, and 5b is a drain electrode.

When constructing the gate electrode into a solar cell structure, the material is as follows:
It may also be amorphous silicon.

However, when polysilicon or amorphous silicon is used as the material of the gate electrode in this way, the threshold value becomes high, so it is difficult to make it smaller than the photovoltaic force.

Due to problems in the manufacturing method (fly-IJ cycles), aluminum cannot be used for the source or drain electrodes (therefore, a multi-Wj 4i1i structure cannot be manufactured). If polysilicon is used for the source electrode or drain electrode, the resistance will increase, making it unsuitable for power applications.

These various problems can be solved by interposing a metal layer directly under the solar cell structure.

This invention was completed based on the above-mentioned knowledge discovered by the inventor, and is characterized in that the gate electrode is composed of a solar cell structural part and a metal layer directly below it. This will be explained in detail below with reference to the drawings.

As shown in Figure 2, the optical input MOS according to this invention)
The gate electrode 14 of the transistor is formed by providing a metal layer 14c directly below the polymer layers 14a and 14b that make up the solar cell structure. For example, solar cell structural parts 14a, 14
If the material of b is a steel plate, metal IEf 14 (
: It is very natural that molybdenum is chosen as the material of
When the material of the solar cell structural parts 14a, 14b is amorphous silicon, aluminum is preferably selected as the material of the metal layer 14c. When the substrate 11, such as a silicon semiconductor, is of p-type, the solar cell structural part is usually formed by the upper layer 14a.
is n-type, the lower layer 14) is p-type, and vice versa when the substrate 11 is n-type. In the figure, 12a, '121.
+ is n-type or p-type expansion +1, 13 is insulating oxide film, 1
5a is a source electrode, and 15b is a drain electrode. The solar cell structure portion 14a, I4L+ is made of C on the metal layer 14c.
It is usually grown in one step using VD (vapor phase growth).

This (D optical input MOS + transistor operates as follows. When there is no optical input, as shown in the circuit diagram in Fig. 3, the solar 71
! 'I NrN internal) becomes a capacitor and a diode, and the MOS input is in the state of "0". When there is light input, as shown in the circuit diagram in Figure 4, an electromotive force is generated in the solar cell gate I section (inside the chain line) and a voltage is applied to the gate, so the MOS is operated manually. The state will be as follows.

In this way, the optical input Mos+ transistor of the present invention is gated? Since the li pole is composed of the solar cell structure i'li and a metal layer provided directly below it, the photovoltaic power of the solar cell is applied to the gate oxide film through the metal layer, and Threshold voltage can be reduced. Metal is added to the gate electrode forming material to increase conductivity.
! For reasons such as making it possible to use the same material for wiring when forming gate electrodes, it has become possible to realize a multilayer structure that does not require a dedicated area for solar cells, and a small one-chip optical input MO5) transistor becomes possible.

The optical input MO3I- transistor according to the present invention can be an MO3+ transistor that can be directly controlled by optical communication, and can also be used as a relay or switching element. Therefore, it is possible to realize optical input power control) and transistors.

By the way, as shown in FIG. 5, an n-swell diffusion layer and a p-swell diffusion layer are formed in the silicon wafer 21, and a U-shaped border 12 is formed on the upper surface of the wafer 2I, and an insulating oxide film 23 is formed on the surface thereof. It has been considered to integrate MO3+ transistors vertically by forming the ζ gate 1-electrode 24 through them, thereby increasing the density of one circuit. In the figure, 25a
is the source electrode, and 25b is the drain electrode. At this time, it is necessary that the U-shaped groove 22 described in "1" be made with sufficient thickness. However, when performing iJt using a heterogeneous etching solution,
In the conventional edging method, it is difficult to control both the absolute value and uniformity of the edging depth, and in addition, it is difficult to control the absolute value and uniformity of edging depth. It has the disadvantage of being lazy.

This is silicon! (Using a silicon wafer in which an epitaxial single crystal 33 is grown on a plate 31, a U having a curved bottom surface at the boundary surface as shown in FIG. 6) is used.
The problem is solved by creating the shaped groove 34. That is, by selectively oxidizing the surface of the silicone brackets 4 & 31, 5iOzl 132, which will become the bottom part of the groove, is created as shown in FIG. 7(a).

Next, as shown in FIG. 7 (bl), an epitaxy layer 33 is formed on the substrate 31J-.
The upper part of 32 has many defects, so if you use a strong etching solution such as one whose main ingredients are nitric acid and hydrofluoric acid,
Selective etching becomes possible.

Therefore, as shown in FIG. 7 (C1), only this portion 33' is removed by etching.
It is important to keep the amount within a limit that does not eliminate the Oz layer 32. Finally, using a weak etching solution such as one containing only hydrofluoric acid as a main component, 5iOz circumference 32 of the bottom of the groove is etched.
Remove by etching. As a result, a smooth curved surface is created at the site where the 5iOzJEf was removed, and a highly accurate U-shaped groove 34 is formed.

In the above method, since 5iQ2JfiW is used as the etching end point (stopper), the etching depth can be easily controlled. Since the removal trace of 5i021E1 formed by selectively oxidizing the silicon substrate surface is made to be the bottom of the U-shaped groove, the bottom surface of the U-shaped groove becomes a smooth curved surface. Therefore, when a high-voltage power transistor is made using the obtained U-shaped silicon wafer with li'+I, the concentration of electric field at the corners can be alleviated, and the breakdown voltage can be improved.

[Brief explanation of drawings]

Fig. 1 is a structural explanatory diagram of a MOS transistor in which Kate 711 has a solar cell structure, and Fig. 2 is a structural explanatory diagram showing an embodiment of a light input Mo5t transistor according to the present invention.
FIGS. 3 and 4 show optical input MO3+ according to the present invention.
- An explanatory diagram of the operation of a transistor, Figure 5 is a horizontal dipping diagram of a vertical MO3+ transistor, Figure 6 is a structural diagram of a silicon substrate surface with a good 10 degree U-shaped groove, and Figure 7 ( al
~(dl is an explanatory diagram of the process of making the silicone Z wafer in FIG. 6. 11...Silicon substrate 12a, 12b...Diffusion layer 13...Insulating oxide film 14...GeI/electrode 14
a114b...Solar cell structural part 14c...Gold J
jri l threat 15a...source power 4fi15b...
Drain'/llll Special Fraud Applicant Matsushita Electric Works Co., Ltd. Representative Patent Attorney Takehiko Matsumoto Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 11gflJ March 4, 1958 Commissioner of the Japan Patent Office 1, Indication of the case +1/, 11157 Patent Application No. 134021 2, Name of the invention Optical input MO3I-Ran resistor 3, ? Relationship with the case to be corrected (related) Patent applicant Address: 1048 Kadoma, Kadoma City, Osaka Prefecture Name (583) Matsushita Electric Works Co., Ltd. Representative: Iku Kobayashi 4, no agent 6, subject of amendment Detailed explanation of the invention in the specification, Part 7, Contents of the amendment (11) In the first line of page 6 of the specification, between “Considered.” structure, the light-receiving area of the solar cell structure increases and the amount of light received increases.
3+・Ran resistor). ” is inserted.

Claims (3)

[Claims] (1) Optical input M, O characterized in that the gate electrode is composed of a solar cell structural part and a metal layer directly below it.
3+・Rangista. (2) The optical input Mos+ transistor according to the first item of the scope of patent Nrl, wherein the material of the solar cell structure 01) is polysilicon, and the material of the metal layer is molybdenum. (3) The optical input MO3I transistor according to claim 1, wherein the material of the solar cell structure is amorphous silicon, and the material of the metal layer is aluminum.