JPS5925577A - Switching regulator - Google Patents

Abstract

PURPOSE:To enhance precision of the voltage and stability of output of the titled device by a method wherein switching of high resolving power is performed using a delay line having resolving power of high precision and a selector to select output thereof. CONSTITUTION:A DC voltage applied between input terminals A, B is supplied to load 8 through an input filter 1, a switching transistor 2, an energy storing coil 3, a fly-wheel diode 4, and a smoothing capacitor 5. Delay time of the delay line 17 is selected by the selector 16, and by synthesizing the output thereof and the output of a counter 13 by gate 18, the switching pulse of the switching transistor 2 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching regulator device that digitally controls the pulse width and stabilizes the output voltage to a desired voltage using a delay line.

Conventionally, this type of switching regulator device has been constructed as shown in FIG. In Figure 1, (1) is an input filter, (2) is a switching transistor, I3
To 1? Energy storage coil, (4) is a freewheeling diode, (5) is a smoothing capacitor, (61.

(7) is the voltage detection resistor, (8) is the load, (91)'
! Transistor (driver circuit that drives 11, αI
is a converter that converts an analog signal into a digital signal, aυ is a digital switch for voltage setting, (la is a subtracter, θ31 is a counter, (I4) is a clock generator,
A9 is a divider that divides the signal generated by the clock generator I to obtain a basic switch frequency for driving the transistor (2).

Next, the operation of this device is shown in Figure 2, which shows the operation waveforms of each part.
FIG. 3 shows a logic diagram and will be explained in detail.

When transistor (2) becomes conductive (ON) with direct current applied between input terminals A and B in Fig. 1, energy is accumulated in the coil (3) and capacitor (5), and transistor (2) becomes non-conductive (ON). OFF), the diode (
4) becomes conductive, the energy stored in the coil (3) and capacitor (5) is released, and a desired voltage can be applied to the load (8) by the 0N10FF ratio of the transistor (2). The voltage of this load (8) is
The waveform in (a) of the figure is divided by the waveform resistor (6) and the resistor (7), and this divided voltage becomes a digital signal in the ~Φ converter αα (FIG. 3(f)). The output of this A/'D converter aQ is input to the (+) terminal of the subtractor α. On the other hand, the output (gl in Fig. 3) set by the digital switch 0υ is input to the (-) terminal of the subtracter O2, and the output (Q) of the subtractor a2 is fitted into the converter (1 (I) as the output signal in Fig. 3). (f)
The difference signal (h) in FIG. 3 appears between the output signal (gl) of the digital switch αυ and the output signal (gl in FIG. 3). This difference signal is input to the data terminal (DI) of the counter The clock iY generated at I is counted, and this count number is calculated by (j
The output pulse width of the frequency divider 9 becomes narrower by l, and this pulse drives the transistor (2) via the driver (9). Operating in this way, the voltage applied to the load (8) is A
Control should be performed so that the difference between the output of the /p converter αα and the digital switch 0υ becomes zero.

At this time, the input voltage (Via) and the voltage (VOOT) applied to the load (8) have a relationship as shown in equation (1).

Here, T8 is the basic time width of the frequency divider 0!9, TO is the clock time, Ω is the count number of the counter 0, and the nature switch aG
This is the difference between the output of and the output of digital switch αυ. Further, the accuracy of the voltage applied to the load (8) at this time is as follows from equation (1).

TC A = (1st Saturday) Vout・・・・・・・・・・・・
(2) S Here, A is the applied voltage accuracy of the load (8). In this way, the %EE applied to the load (8) depends on the clock time (Tc) and the basic time width (Ts) of the division period O9.

By the way, the response time of currently used integrated circuits is about IQ n8 for high speed gate circuits. Therefore, the clock time that can actually be used in equation (2) is 20n(8), and this frequency corresponds to 50 MHz. Considering the expected increase in the frequency of switching regulators in the future, for example, if the switching frequency is set to about 500kHz, the basic time width of the division period will be 112μ high, and therefore the output voltage accuracy will be 200μ/2μ5ec = ont, which will be sufficiently stable. You won't be able to get a degree.

This invention was made to improve these nine drawbacks, and uses a delay line with high precision resolution and a selector that reversely prints the delay line (in parallel with the conventional counter, clock generator, and frequency divider circuit). This allows high-resolution switching to be performed by operating the switch.

Next, an embodiment of the present invention is shown in FIG. 4 and will be described in detail below.

In Figure 3, αe is a selector and the delay line α
This is to select the delay time of η, and Q is the AN that combines the output of cowl 0 and the output of delay line 0η.
This is the D gate. Figure 5 shows the structure of the delay line (1?), where dV is the power terminal, (IG is the ground terminal, and do is the output terminal.

d1 to dn are delay terminals. or Co+, (
j02...Con is the inductor that makes up the delay, LOI, LO2...LOΩ is the inductor that makes up the delay, and the two sides are the delay time. Also S1. S2...Sn is an equidynamic representation of the output of the selector. The output +do of the delay line 0D is at the VCC level when 511S2...Sn is open. Next, when 81 is closed, t
The dO terminal becomes zero after a1 time delay j, d1=V; 〒J〒 Also, when S2 is closed, the dO terminal becomes zero after a td2 time delay. To operate in this way, by appropriately selecting the output of the selector, it is possible to form a Ωtit time of Ωtit. (
8) is possible. Like this, the delay line (l
Since high-resolution switching is possible by using η, the output of delay line a7) and counter 03
Counter 0 is created by combining the outputs of
clock time (TC)'. If the driver (9) is driven by the output of the gate 08, a very high-resolution pulse switch is possible.

Equation (3) shows the equation for the applied voltage accuracy of load (8) according to the present invention. In the case of increasing the frequency in this invention, for example, if the switching frequency is increased to 500 kHz,
At this time, the basic time width is reduced by 2μ from 1, and if a 200pSai step delay line is used for td1, the output voltage accuracy is 200p%/2μbba = o, ooot.
It can be seen that sufficient stability can be obtained.

Since the switching regulator device according to the present invention operates as described above, even in switching regulators that are digitally controlled, voltage stability is maintained due to the delay time accuracy of the delay line without being affected by the clock time determined by the element (integrated circuit). You can get it.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional switching regulator device, Fig. 2 is an operating waveform of each part in Fig. 1, Fig. 3 is a logic diagram of Fig. 1, and Fig. 4 is a block diagram of a switching regulator device of the present invention. , FIG. 5 is a block diagram of the delay line. In the figure, (1) is a filter, (2) is a transistor, and (3)
is the coil, (4) is the diode I (511-1 capacitor, (61, (7) is the resistor, +811'!load, (
9) is a driver circuit, 011 converter, αυi switch, O3 is a subtracter, u3 is a counter, 0-1 clock generator, 09 is a frequency divider, OI-ma selector, Q71i1
Delay line, uit gate. In the drawings, the same or corresponding parts are designated by the same reference numerals. Agent Makoto Kuzuno

Claims (1)

[Scope of Claims] A converter for converting the output of the switching regulator into a digital signal, a digital switch for digitally setting a reference voltage, and a subtractor for comparing and subtracting the output of the converter with a set value of the digital switch. a counter connected to one of the two output terminals of the subtracter, a clock generator and a one-way divider for driving the counter, and a selector connected to the other output terminal of the subtractor. A switching regulator device comprising: a delay line controlled by the selector; and a gate for synthesizing the output of the delay line and the output of the counter, the output of the gate being connected to a driver of a switching transistor.