JPS5928073B2 - Method for forming electrodes for semiconductor devices - Google Patents
Method for forming electrodes for semiconductor devicesInfo
- Publication number
- JPS5928073B2 JPS5928073B2 JP53165782A JP16578278A JPS5928073B2 JP S5928073 B2 JPS5928073 B2 JP S5928073B2 JP 53165782 A JP53165782 A JP 53165782A JP 16578278 A JP16578278 A JP 16578278A JP S5928073 B2 JPS5928073 B2 JP S5928073B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- etching
- alloy
- layer
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000005530 etching Methods 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 13
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910000676 Si alloy Inorganic materials 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- DKNPRRRKHAEUMW-UHFFFAOYSA-N Iodine aqueous Chemical compound [K+].I[I-]I DKNPRRRKHAEUMW-UHFFFAOYSA-N 0.000 claims description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 claims description 2
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 claims description 2
- 239000002253 acid Substances 0.000 claims 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 description 18
- 239000000956 alloy Substances 0.000 description 18
- 229910001020 Au alloy Inorganic materials 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 3
- 229910052740 iodine Inorganic materials 0.000 description 3
- 239000011630 iodine Substances 0.000 description 3
- NLKNQRATVPKPDG-UHFFFAOYSA-M potassium iodide Chemical compound [K+].[I-] NLKNQRATVPKPDG-UHFFFAOYSA-M 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Landscapes
- Led Devices (AREA)
Description
【発明の詳細な説明】
本発明は、半導体基板表面上の選択された部分に金シリ
コン（Ａｕ／Ｓｉ）合金あるいは金ゲルマニウム（Ａｕ
１０ｅ）合金よりなる電極を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for depositing gold-silicon (Au/Si) alloy or gold-germanium (Au) on selected portions on the surface of a semiconductor substrate.
10e) A method of forming an electrode made of an alloy.
Ａｕ／５１合金あるいはＡｕ１０ｅ合金は周知のよ ３
５うに皿−Ｖ化合物半導体装置のｎ型領域に形成される
電極の材料として広く使用されている。Au/51 alloy or Au10e alloy is well known.3
5. Sea urchin dish-V It is widely used as a material for electrodes formed in the n-type region of compound semiconductor devices.
■一Ｖ化合物半導体装置が発光ダイオードである場合、
発光ダイオードの裏面側を形成するｎ型領域への電極形
成は裏面側における光の反射効率を高めるためその全面
に対してはなされず、部分的に形成される。第１図は、
このような関係で裏面側に電極が形成された発光ダイオ
ード基板の状態を示す図であり、図示するように発光ダ
イオード基板の裏面側を形成するｎ型領域１に対してＡ
ｕ／５１合金あるいはＡｕ／Ｇｅ合金よりなる電極２が
形成されている。■If the 1V compound semiconductor device is a light emitting diode,
Electrodes are not formed on the entire surface of the n-type region forming the back side of the light emitting diode in order to increase the light reflection efficiency on the back side, but are formed partially. Figure 1 shows
This is a diagram showing a state of a light emitting diode substrate in which an electrode is formed on the back side in such a relationship, and as shown in the figure, A
An electrode 2 made of u/51 alloy or Au/Ge alloy is formed.
このような部分電極２は、先ずｎ型領域１の裏面全域に
Ａｕ／Ｓｉ合金あるいはＡｕ１０ｅ合金の蒸着によつて
電極層を形成したのち、この電極層をヨードエッチ液等
を用いて選択的に除去することによつて形成される。Such a partial electrode 2 is made by first forming an electrode layer over the entire back surface of the n-type region 1 by vapor deposition of Au/Si alloy or Au10e alloy, and then selectively etching this electrode layer using an iodine etchant or the like. formed by removing.
ところで、ｎ型領域上にＡｕ／５１あるいはＡｕ／Ｇｅ
合金を蒸着した場合、この蒸着工程で両者の境界面に変
成層が形成されるが、上記のエッチング処理では境界面
の変成層まで除去することができず、実際に形成された
発光ダイオード基板の断面構造は第２図で示すように、
ｎ型領域１の表面全域に変成層３が存在し、この変成層
の上に電極２の形成された構造となる。なお、図中４は
ｐ型領域、５は同領域に形成された通常の電極である。
すなわち、従来の電極の形成方法によつてＡｕ／Ｓｉあ
るいはＡｕ／Ｇｅ合金の部分電極を形成した場合には上
記のように変成層が残るところとなり、所定の裏面反射
効率を得ることができなくなるおそれがあつた。本発明
は、Ａｕ／５１あるいはＡｕ／Ｇｅ合金を蒸着して電極
金属層を形成した場合にこの電極金属層と半導体基板と
の境界面に形成される変成層を、最終的に形成される部
分電極直下を除く他の部分上から除去することのできる
半導体装置用電極の形成方法を提供するものであつて、
本発明の方法の特徴は、燐酸、硝酸および弗酸を含む特
有の第１のエッチング液とヨウ素およびヨウ化カリを含
む第２のエツチング液とを準備し、部分電極を形成する
ためにＡｕ／Ｓｉ合金あるいはＡｕ／０ｅ合金の電極層
を選択的に除去するにあたり、第１のエツチング液によ
るエツチング処理と第２のエツチング処理とそれぞれを
少くとも１回づつ柚し、このエツチング処理ののち、残
存する電極層をマスクとして第１のエツチング液による
エツチング処理を施すことにより電極層に覆われること
なく露呈する変成層を除去し、所定の形状をもつ部分電
極を形成するところにある。By the way, Au/51 or Au/Ge is formed on the n-type region.
When an alloy is vapor-deposited, a metamorphic layer is formed at the interface between the two during this vapor deposition process, but the etching process described above cannot remove the metamorphic layer at the interface, and it is difficult to remove the metamorphic layer at the interface. The cross-sectional structure is shown in Figure 2,
A metamorphic layer 3 exists over the entire surface of the n-type region 1, and the electrode 2 is formed on this metamorphic layer. In the figure, 4 is a p-type region, and 5 is a normal electrode formed in the same region.
In other words, if a partial electrode of Au/Si or Au/Ge alloy is formed using the conventional electrode formation method, a metamorphic layer will remain as described above, making it impossible to obtain the desired backside reflection efficiency. I was afraid. In the present invention, when an electrode metal layer is formed by vapor-depositing Au/51 or Au/Ge alloy, the metamorphic layer that is formed at the interface between the electrode metal layer and the semiconductor substrate is removed from the finally formed portion. Provided is a method for forming an electrode for a semiconductor device that can be removed from above other parts except directly below the electrode, the method comprising:
A feature of the method of the present invention is that a unique first etching solution containing phosphoric acid, nitric acid and hydrofluoric acid and a second etching solution containing iodine and potassium iodide are prepared and Au/ When selectively removing the Si alloy or Au/Oe alloy electrode layer, the first etching process and the second etching process are performed at least once each, and after this etching process, the remaining etching is removed. By performing an etching process using a first etching solution using the electrode layer as a mask, the metamorphic layer exposed without being covered by the electrode layer is removed, and a partial electrode having a predetermined shape is formed.
以下に実施例を示して本発明の半導体装置用電極の形成
方法について説明する。The method for forming an electrode for a semiconductor device of the present invention will be described below with reference to Examples.
エツチング処理に用いる第１のエツチングとして燐酸、
硝酸、弗酸および水を容量比で５：３：１：１の割合で
混合したものを、また、第２のエツチング液として周知
のヨードエツチング液（ヨウ素：ヨウ化カリ：水＝２５
９：５０９： ５００ｃｃ）を準備する。As the first etching agent used in the etching process, phosphoric acid,
A mixture of nitric acid, hydrofluoric acid, and water in a volume ratio of 5:3:1:1 was used as a second etching solution, and a well-known iodine etching solution (iodine: potassium iodide: water = 25
9:509: Prepare 500cc).
そして、ＡＵ／／Ｓ１合金あるいはＡｕ／Ｇｅ合金より
なる電極層がｎ型領域上の表面全域に形成され、さらに
この電極層上が所定のパターン形状のマスクにより覆わ
れた発光ダイオード基板を先ず第１のエツチング液中へ
浸漬しマスクにより覆われることなく露呈する電極層を
所定の時間にわたりエツチングする。この処理により、
酸化物、合金物層等の不要な層がほぼ完全に除去される
。次いで、第２のエツチング液中へ発光ダイオード基板
へ浸漬し電極層を完全に除去する。以上の過程を経るこ
とにより、第２図で示したのと同様の状態が得られる。
ところで、第１のエツチング液による処理を先行させる
理由は、電極層の蒸着時に電極層表面にシリコンもしく
はゲルマニウムの酸化物、基板物質およびこれらの酸化
物ならびに電極形成用合金を含む合金物層が形成され、
これの除去が第２のエツチング液によつては比較的困難
であるところにある。Then, an electrode layer made of AU//S1 alloy or Au/Ge alloy is formed over the entire surface of the n-type region, and the light emitting diode substrate is covered with a mask having a predetermined pattern shape. The electrode layer exposed without being covered by the mask is etched for a predetermined time by immersing the electrode layer in the etching solution of No. 1. With this process,
Unnecessary layers such as oxide and alloy layers are almost completely removed. Next, the light emitting diode substrate is immersed in a second etching solution to completely remove the electrode layer. By going through the above process, a state similar to that shown in FIG. 2 is obtained.
By the way, the reason why the treatment with the first etching solution is performed in advance is because an alloy layer containing silicon or germanium oxide, the substrate material, these oxides, and an electrode-forming alloy is formed on the surface of the electrode layer during vapor deposition of the electrode layer. is,
This is relatively difficult to remove using the second etching solution.
このようにして電極層を選択的にエツチングしたのち、
さらに発光ダイオード基板を第１のエツチング液中へ浸
漬し電極層の除去された部分に露呈する変成層を除去す
る。変成層の組成は上記の合金物層の組成と殆んど同じ
であり、第２のエツチング液によつてはこれを除去する
ことは困難である。なお、第１のエツチング液のＡｕ／
Ｓｉ合金あるいはＡｕ／Ｇｅ合金に対するエツチング作
用は極めて弱く、したがつて、変成層のエツチング時に
は残存するＡＵ／／Ｓ１合金あるいはＡｕ／Ｇｅ合金の
電極がエツチングのマスクとして作用する。第３図は以
上の処理を経て部分電極の形成された発光ダイオード基
板を示す図であり、図示するように部分電極２の直下に
は変成層３が残るものの他部分からは変成層が完全に除
去され、部分電極２の形成部を除いてｎ型領域１の表面
が露呈する。After selectively etching the electrode layer in this way,
Further, the light emitting diode substrate is immersed in the first etching solution to remove the metamorphic layer exposed in the portion where the electrode layer has been removed. The composition of the metamorphic layer is almost the same as that of the alloy layer described above, and it is difficult to remove it using the second etching solution. Note that the Au/
The etching effect on the Si alloy or Au/Ge alloy is extremely weak, so when etching the metamorphic layer, the remaining AU//S1 alloy or Au/Ge alloy electrode acts as an etching mask. FIG. 3 is a diagram showing a light emitting diode substrate on which partial electrodes have been formed through the above processing.As shown in the figure, the metamorphic layer 3 remains directly under the partial electrode 2, but the metamorphic layer is completely removed from other parts. The surface of the n-type region 1 is exposed except for the portion where the partial electrode 2 is formed.
また、第１のエツチング液は発光ダイオード基板そのも
のには殆んど作用しないため、露展するｎ型領域の表面
は阻面化されず、光の反射効率のすこぶる良好な面状態
を呈する。以上説明してきたところから明らかなように
、本発明によれば、ＡＵ／Ｓｌ合金あるいはＡｕ／Ｃ３
ｅ合金よりなる電極層を選択エツチして部分電極を形成
するにあたり、電極層と半導体基板との境界面に形成さ
れた変成層の部分電極となる電極層部分の下に位置する
変成層部分を除く他の全てを確実に除去することができ
、この変成層の存在によつてもたらされる不都合が排除
される。Further, since the first etching liquid hardly acts on the light emitting diode substrate itself, the surface of the exposed n-type region is not blocked and exhibits a surface condition with extremely good light reflection efficiency. As is clear from the above explanation, according to the present invention, AU/Sl alloy or Au/C3
When selectively etching the electrode layer made of e-alloy to form a partial electrode, the metamorphic layer portion located below the electrode layer portion that will become the partial electrode of the metamorphic layer formed at the interface between the electrode layer and the semiconductor substrate is etched. All but one of the metamorphic layers can be reliably removed, eliminating the inconvenience caused by the presence of this metamorphic layer.
なお、以上の説明では電極層のエツチングが第１および
第２のエツチング液を各１回作用させることによりなさ
れる場合を示したが、この処理を経てなおエツチングが
不十分であるときには上記のエツチング処理をさらにく
り返して帷せばよい。Note that in the above explanation, the case where the electrode layer is etched by applying the first and second etching solutions once each is shown, but if etching is still insufficient after this treatment, the above etching method is applied. All you have to do is repeat the process.
第１図は裏面側に部分電極が形成された発光ダイオード
基板を示す図、第２図はＡＵ／Ｓｌ合金あるいはＡｕ／
Ｇｅ合金部分電極を従来の方法で形成した発光ダイオー
ド基板の断面構造を示す図、第３図は本発明の方法によ
りＡＵ／Ｓｌ合金あるいはＡｕ／Ｇｅ合金の部分電極が
形成された発光ダイオードの断面構造を示す図である。
１・・・・・・ｎ型領域、２・・・・・・電極、３・・
・・・・変成層、４・・・・・・Ｐ型領域、５・・・・
・・電極。Figure 1 shows a light emitting diode substrate with a partial electrode formed on the back side, and Figure 2 shows an AU/Sl alloy or Au/
Figure 3 shows a cross-sectional structure of a light emitting diode substrate with a Ge alloy partial electrode formed by the conventional method, and Figure 3 shows a cross section of a light emitting diode with an AU/Sl alloy or Au/Ge alloy partial electrode formed by the method of the present invention. It is a figure showing a structure. 1...n-type region, 2...electrode, 3...
... Metamorphic layer, 4 ... P-type region, 5 ...
··electrode.
Claims (1)
ルマニウム合金よりなる電極層が形成された半導体基板
の電極層を選択エッチングして所定の電極パターンを有
する電極を形成するにあたり、燐酸、硝酸および弗酸を
含む第１のエッチング液による第１次のエッチング処理
と、ヨウ素およびヨウ化カリウムを含む第２のエッチン
グ液による第２次のエッチング処理を順次施し電極層を
選択的にエッチングしたのち、さらに前記第１のエッチ
ング液によるエッチング処理を施し前記電極層の除去さ
れた部分に残存する変成層を除去することを特徴とする
半導体装置用電極の形成方法。1. When selectively etching the electrode layer of a semiconductor substrate on which an electrode layer made of gold-silicon alloy or gold-germanium alloy is formed on at least one surface to form an electrode having a predetermined electrode pattern, phosphoric acid, nitric acid and fluorocarbon After selectively etching the electrode layer by sequentially performing a first etching treatment using a first etching solution containing acid and a second etching treatment using a second etching solution containing iodine and potassium iodide, A method for forming an electrode for a semiconductor device, comprising performing an etching process using the first etching solution to remove a metamorphic layer remaining in the removed portion of the electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53165782A JPS5928073B2 (en) | 1978-12-27 | 1978-12-27 | Method for forming electrodes for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53165782A JPS5928073B2 (en) | 1978-12-27 | 1978-12-27 | Method for forming electrodes for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5591187A JPS5591187A (en) | 1980-07-10 |
| JPS5928073B2 true JPS5928073B2 (en) | 1984-07-10 |
Family
ID=15818904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53165782A Expired JPS5928073B2 (en) | 1978-12-27 | 1978-12-27 | Method for forming electrodes for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5928073B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62104082A (en) * | 1985-07-25 | 1987-05-14 | Nec Corp | Forming method for back surface electrode |
| JPS6384125A (en) * | 1986-09-29 | 1988-04-14 | Nec Corp | Method for forming electrode of compound semiconductor |
| JP3399814B2 (en) * | 1997-11-27 | 2003-04-21 | 科学技術振興事業団 | Method for manufacturing fine projection structure |
-
1978
- 1978-12-27 JP JP53165782A patent/JPS5928073B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5591187A (en) | 1980-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3867218A (en) | Method of etching a pattern in a silicon nitride layer | |
| JPH0121618B2 (en) | ||
| JPS5928073B2 (en) | Method for forming electrodes for semiconductor devices | |
| US4052253A (en) | Semiconductor-oxide etchant | |
| US3639186A (en) | Process for the production of finely etched patterns | |
| JPS5839374B2 (en) | Semiconductor substrate processing method | |
| US4040893A (en) | Method of selective etching of materials utilizing masks of binary silicate glasses | |
| US3947304A (en) | Etching of group III-V semiconductors | |
| JPH11312665A (en) | Surface roughening method for semiconductor substrate | |
| JPS5912021B2 (en) | Manufacturing method of semiconductor device | |
| JP2830414B2 (en) | Method of forming MES structure electrode | |
| CN115206799B (en) | A etching process with a top layer of metallic nickel. | |
| KR900008408B1 (en) | Electrode formulating method for iii-v family compound semiconductor device | |
| JPS6155780B2 (en) | ||
| JPS5816074A (en) | Etching method for gold or gold alloy film | |
| JPH0226790B2 (en) | ||
| US3505132A (en) | Method of etching semiconductive devices having lead-containing elements | |
| JP4355785B2 (en) | Semiconductor device manufacturing method and semiconductor device manufacturing method | |
| JP3126262B2 (en) | Etching method of gold or gold alloy film | |
| JPS58192338A (en) | Semiconductor device and its manufacture | |
| JPS6310894B2 (en) | ||
| JPS55153332A (en) | Manufacture of gallium arsenide semiconductor device | |
| JP3729437B2 (en) | Method for manufacturing compound semiconductor device | |
| CN121096868A (en) | Semiconductor structure and forming method thereof | |
| JPS583250A (en) | Manufacture of semiconductor device |