JPS5928286A - Cache buffer controller - Google Patents

Abstract

PURPOSE:To improve the performance of a titled device, by increasing chances for acceptance of access requests to a cache buffer, while resetting the bit corresponding to a column and at the same time regarding the hit decision of a comparator as a mishit decision. CONSTITUTION:A cache control circuit 6 is designated and read out with the 2nd block address E of an access address A when an access request H is given and a comparator 3 delivers a hit signal F1 and a hit column information F2. Then the contents L held in a column memory 5 are compared with the hit column information as well as the set information for each pot. When a bit of the coincident set state is detected from the comparison, the signal F1 is converted into a signal equivalent to a mishit signal G. When this signal or the mishit G delivered from the comparator 3 exists, a mishit signal Q is delivered as a real mishit signal. At the same time, the reset column information M is delivered to the memory 5 to reset the coincident bit to ''0''.

Description

[Detailed description of the invention] The present invention relates to a cache buffer control device.

In particular, it includes a plurality of data processing devices that share a main memory (hereinafter referred to as main memory), and at least one of these data processing devices holds copies of a plurality of data blocks in the main memory over at least one column per address. The present invention relates to a cache buffer control device in a data processing system including a cache buffer and a cache buffer control device.

operating speed gear between data processing device and main memory;
As is well known, in order to fill the gap between the two, a cache buffer consisting of a high-speed, small-capacity memory is often provided between the two. The main memory is divided into blocks of a fixed capacity, the data of multiple blocks among these blocks are held in a cache buffer, and the block address information indicating which data block of the main memory is held in the cache buffer is stored. Write to the tag memory location corresponding to the location determined by the address and column of the cache buffer.

When a data processing device that uses the cache buffer (hereinafter referred to as the data processing device) accesses the cache buffer, it first accesses the tag memory and checks whether the data block containing the access address is held in the cache buffer. This is checked by referring to the block address information held in the tag memory. If it is found that the data is not retained (miss), the data processing device reads the data from the main memory, writes the data block rich in this data to the specified position of the cache buffer according to a predetermined procedure, and writes the new data block to the cache buffer. It is necessary to write the block address information for the loaded data block to the tag memory location corresponding to the cache buffer replacement device. The probability of a miss is usually designed to be on the order of a few percent.

On the other hand, multiple data processing devices share the main memory, such as a data processing system equipped with an input/output control device in addition to a central processing unit with a cache buffer, or a multiprocessor system that includes at least one processor with a cache buffer. In a data processing system, it is necessary to reflect the memory access operations of other data processing devices (data processing devices other than the data processing device) in updating the tag memory described above. In other words, if another data processing device performs a store access to the main memory, the tag memory's self-identification for the cache buffer will be incorrect, so the block address information held at the location in the tag memory will be You will need to disable it.

When partially invalidating a cache buffer as described above, a first step of accessing the tag memory is required to check whether the data block in question is held in the cache buffer. If it is found that the data block is held in the cache buffer, a second step of access to the tag memory is followed to perform a commitment to the tag memory as an invalidation of the data block.

Naturally, when accessing the cache buffer 5- from the data processing device, a first step access to the tag memory is required in order to check for heat dissipation hits and misses, just like when invalidating, and the main memory is shared. As the number of data processing devices increases, competition between access requests and invalidation requests becomes a problem for acquiring access rights to the tag memory.

A conventional cache buffer control device of this type includes a tag memory that holds block address information for a data block held by a cache buffer at a position corresponding to a position determined by an address and a column of the cache buffer;
When the cache buffer receives an access request or a standstill/validation request from another data processing device in conjunction with execution of a store access to the main memory, the cache buffer may perform the above operations based on the block address information read from the tag memory. When the comparator circuit makes a hit determination, the addressable stack stores positional information regarding the current location of the tag memory over at least six levels according to a predetermined procedure, e.g., first-in-first-out (F'IFO). If positional information is stored in either level of the circuit or stack circuit, the block address information of the tag memory specified by this positional information is invalidated according to a predetermined procedure, for example, FIFO. and a tag memory control circuit.

In such a conventional configuration, for example, the priority for accepting access requests from the data processing device is set as follows:
The contention problem for the first step access to the tag memory described above can be solved by adopting a method that gives a higher priority to accepting J1 validation requests from other data processing devices, but normally when executing unilateral validation, Since there is no solution for the second step access that is processed consecutively to the first step access, this second step access will inhibit the tag memory access in response to the access request, and will further reduce the performance of the data processing device. It has the disadvantage of lowering

An object of the present invention is to provide a cache buffer control device that improves the performance of the data processing device.

The device of the present invention includes a plurality of data processing devices that share a main memory, and at least one of these data processing devices has a cache buffer and cache buffer control for holding copies of a plurality of data blocks in the main memory over at least one column per address. The cache buffer control device in the data processing system includes: a tag memory that holds block address information regarding the data block held by the cache buffer at a position corresponding to a position determined by an address and a column of the cache buffer; , Check the block address information read from the tag memory when a validation request is made in conjunction with door access execution to determine whether there is a hit or miss. A column memory that holds a bit in a set state, and a column memory that is read out based on the hit column and the read address to the tag memory at this time when the comparison circuit judges that the access request is hit. A cache control circuit is provided, which compares the stored content column by column and, if there is a column that matches, resets the bit corresponding to the column and makes the hit determination in the comparison circuit the same as the miss determination. shall be.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention together with a cache memory 8 and a main memory 9. As shown in FIG.

The main memory 9 is divided into 9-4.09611L (K=1024) blocks, each having 16 addresses, and 256 of these 4,096 blocks (data blocks). data is held in the cache buffer 78. cache buffer 8
has 64 addresses each consisting of 4 columns, and holds a copy of the data of one data block at each of the 256 positions determined by the address and column.

This embodiment includes a switching circuit 1, a tag memory 2, and a comparison circuit 3.
, a replacement column designation circuit 4, a column memory 5, a cache control circuit 6, and a tag memory control circuit 7.

The switching circuit 1 selects the access address A from the data processing device concerned and the invalidation request address B from another data processing device.
Then, only one of these two addresses is selected, and the block address is divided into a first block address D and a second block address E and output. The first block address D and the second block address E are respectively composed of 16 bits and 6 bits, and a total of 10 to 22 bits specify one of the 4o9m data blocks. The second block address E is a tag memory '2+replacement column specifying circuit 4, column memory 5, and carriage Yuba, which will be described below.

This is the access address for FPU8.

The tag memory 2 is 256 which is held by the cache buffer 8.
Four first block addresses D for each data block are held at each of the 64 addresses specified by the second block address E that is paired with the first block address D.

The comparator circuit 3 converts the first block address D output from the switching circuit 1 into the content held in the tag memory 2 (first block address) that is specified and read by the second block address E that is paired with the first block address D. Compare everything. As a result of the comparison, if the contents match any of the contents held in the tag memory 2, the hit signal Fl and the hit column information F2 are sent, and if the contents do not match any of the contents held in the tag memory 2, the request K is sent. The comparison circuit 3 outputs the hit signal F1 and the hit column information p for the invalidation request address B.
2, the bit corresponding to this hit column information F2 is set to a ("1"), and is written to the address specified by the second block address E of the invalidation request address B and held. This retained content is stored at the second block address E of access address A when tag memory 2 and cache buffer 8 are accessed.
The data is read from the address specified by . The column memory 5 enters the reset state ("O
” ).

When there is an access request H and the comparator circuit 3 outputs the hit signal F1 and the hit column information F2, the cache control circuit 6 outputs the contents held in the column memory 5 specified by the second block address E of the access address A and read out. Compares the hit column information and the set state bit by bit.

If there is a matched set bit as a result of the comparison, the hit signal F1 is changed to a signal equivalent to the miss signal G, and this signal or the miss signal output from the comparator circuit 3 is
When there is a mishit signal G, an unsuitable signal Q is output, and this unsuitable signal Q is used as a true mishit signal. At the same time, reset column information M for resetting the matching bit to ``O'' is output to the column memory 5. Furthermore, when there is no matching bit, the hit signal F1 is output as is as the consecutive signal P.

The replacement column designation circuit 4 reads the replacement column information J from the address designated by the second block address E of the access address A when the access request H, read command U, and unqualified signal Q are input. This replacement column information J is written in accordance with the hit column information F2 each time the serial signal P is input, and is shifted by one bit each time the above reading is performed. This is for specifying the column of the tag memory 2 to be updated with this loading.

13- The tag memory control circuit 7 outputs replacement column information J to the tag memory 2 as a column designation box when the read command U and unsuitable signal Q are input.

FIG. 2 shows a detailed circuit diagram of the switching circuit 1, tag memory 2, comparison circuit 3, column memory 5, and cache control circuit 6 shown in FIG.

The -1' tag memory 2 is constituted by a random access memory 21 of 64@×64 bits/word from the switching circuit 11 and the register 12 (22 bit configuration). Selection of one word out of the 21064 words of the random access memory is performed by the second block address E. The 64 bits that make up 1@ are divided into four columns of 16 bits each, and the first block address D is expressed by these 16 bits.

Comparison circuit 3 has four comparisons 431-32*33 and 34
and gate 35, and column memory 5 has 64 words x 4
It is composed of a bit/word random access memory 51 and 14 gates 52 to 5F, and each bit corresponds to each column 14 of the tag memory 2, replacement column designation circuit 40, and random access memory 43. .

The cache control circuit 6 is composed of seven gates 61-67.

Now, the switch 11 of the switching circuit 1 selects the first address from among the access address A when there is an access request H, and from the invalidation address B when there is an invalidation request B.
The block address D and the second block address E are input into the register 12.

Tag memory 2 specified by second block address E
The contents held in the comparators 31 to 34 of the comparator circuit 3 are read out from each of the four columns of addresses of the random access memory, and compared with the first block address D at this time.

When a match is detected in any of the comparators as a result of the comparison, a hit signal PI (1'') and hit column information 1i'2 are output from the gate 35 (AND circuit).Hit column information F2 is 1. Only the bit is ``ul'' and the remaining 3 bits are ``0'', which is 4-bit data. If no match is detected in any of the comparators, the gate 35 outputs a miss signal G and the hit column information F2 becomes all "'o'".

(1) At the time of invalidation request, invalidation request K is sent to u lj7, access request H is sent to at
This is the case of om. The gate 35 outputs the hit signal Fl to 11
1", the hit column information F as described above.
Since one bit of 2 is 1'', the AND condition is satisfied in the corresponding one of the gates 54 to 57 (AND circuit) of the column memory 5. ul'' is input to the data input terminal DA of the random access memory 51, and is also input to the write enable terminal WE of the random access memory 51 through the corresponding gate of 50 to 5F (OR circuit). As a result, "ul" is written in the position determined by the second block address E at this time and the column specified by "1"'' by the hit column information F2.The random access memory corresponding to the remaining 93 bits, which is u011, is written. Since tt on is input to the write enable terminal WE of column 51, no writing is performed.In other words, the contents held up to that point are held as they are.

Furthermore, when the gate 35 outputs the miss signal G, the hit column information F2 is all tton, so writing is not performed for the same reason as described above. Since the access request H is not input when the invalidation request K is input, all of the gates 61 to 64 (AND circuit) of the cache control circuit 6 are set to 0.
'' is output. As a result, gate 65 (AND circuit)
The AND condition is now satisfied, and the hit signal Fl is output as is through the gate 66 (AND circuit).

(2) At the time of access request, the access request H becomes "ul" and the invalidation request K becomes "0".

In this case, even if the gate 35 sets the hit signal Fl to ``l'', the AND condition is not satisfied in all of the gates 54 to 57 and 0'' is output. is not carried out.

The random access memory 51 is read from the address specified by the second block address E, regardless of the contents of the hit signal F1, and the contents held in the column memory 5 are read out from the cache control circuit 6 (61 to 61). 64
It is compared with the hit column information F2.

The reset column information M, which is the result of this comparison, is
In step 5, the NAND of each bit is taken, and if the reset column information and information M are all uO'', that is, if there is no bit whose contents match between the hit column information F2 and the contents held in the column memory 5. , the gate 66 outputs the hit signal Fl as it is as a continuous signal P.

When the reset column information M is not all 1o'', that is, when there is at least one bit whose contents match between the hit column information F2 and the content held in the column memory 5, the output of the gate 65 becomes 0''. Therefore, the gate 66 outputs the signal P as uO'' regardless of the content of the hit signal 18-Fl.In other words, in this case, even if the hit signal F1 is
The signal P that is a true hit signal even if it is 1" is II
It becomes OII. The negative output of gate 65 is connected to the miss signal (LR) at gate 67 (OR circuit).
is taken, so at this time the unsuitable signal Q is (L
III, and the hit judgment is the same as the miss judgment.

When the reset column information M is not all ``0'', tolpp is output from the gate of the gates 58 to 5B (OR circuit) corresponding to the bits of u1'', so that the corresponding column of the random access memory 51 is Writing is performed by inputting l" to the corresponding write enable terminal WE. However, since the invalidation request K is °'0#, the outputs of all gates 54 to 57 are 4t OII, and the data input terminal DA (10II is input to all. Therefore, It O# is written. In other words, this writing is 111;+ among the contents held in the column memory 5, and the hit column information F2
It is also significant only for bits that are '1'.

In other words, the content held in the column memory 5 that caused the hit signal Fl to be treated as a miss signal G is reset to uOj''.

The serial signal P output from the cache control circuit 6 is supplied to the cache buffer 78, and the data processing device accesses the cache buffer 8. At this time, if the read command U is at O#, writing to the main memory 9 is also performed. Further, when the read command is at, n, the serial signal P causes the replacement column specifying circuit 4 to select the next replacement column for the address specified by the second block address E at this time, using the hit column information F2.
Created based on.

The unqualified signal Q output from the cache control circuit 6 is supplied to the main memory 9, and the data processing device accesses the main memory 9. Read command U is It
At time lII, a copy of the accessed data block in the main memory 9 is read into the cache buffer 8, and is determined by the second block address E at this time and the replacement column information J output from the replacement column designation circuit 4. It is held at the cache buffer 8 location.

When the tag memory control circuit 7 receives the unqualified signal Q and the read command U, it outputs the p column designation R to the tag memory 2 based on the replacement column information J, and then outputs the second block address E and column designation at this time. The first block address D at this time is written in the location of the tag memory 2 determined by the method.

That is, the tag memory 2 is updated in accordance with the above loading.

In addition, both the unsuitable raw signal Q and the read command U are 1″″
At this time, the replacement column information J to be output next in the replacement column designation circuit 4 is set to forward p.

The embodiment shown in FIG. 1 described above has only one tag memory, but it has two tag memories holding the same contents, each of which handles access requests H from the data processing device and other data processing. By sharing the reference processing (the above-mentioned first step access) for the invalidation request K from the device 21-, it is possible to alleviate the conflict between the two requests and improve the processing performance of the data processing system. A cash buffer 7 control device is known.

FIG. 3 is a block diagram showing another embodiment of the present invention in a cache buffer control device having such a configuration, together with a cache buffer 8 and a main memory 9. In FIG.

This embodiment includes a first switching circuit 100 and a second switching circuit 110.
, a first tag memory 200, a second tag memory 210, a first comparison circuit 300, a second comparison circuit 310, a replacement column designation circuit 400, a column memory 500, a cache control circuit 600, and a tag memory control circuit. It is composed of a circuit 700.

In response to the access request H and the invalidation request, the first switching circuit 100 switches only the second block address E of the access address A and the invalidation request address B to the column memory 500. supply

The second switching circuit 110 switches and outputs only the second block address of the access addresses A to g and the invalidated address B in response to a control signal from the tag memory control circuits 7 to 22 that instructs tag memory update. However, when updating the tag memory, the first tag memory 200 and the second tag memory 21
0 are both accessed by the second block address E of the access address A.

Therefore, the first tag memory 200 and the second tag memory 21
0 means that the same content is held in the same location, and each can share the reference processing for the access request H and invalidation request K.

The first comparison circuit 300 and the second comparison circuit 310 are for determining hits and misses for the access request H and invalidation request K, and extracting hit columns, respectively.

The other circuits are similar to the corresponding circuits in the embodiment shown in FIG.

According to the present invention, by employing the above-described configuration, even if it is known that the data in question is held in the cache buffer, invalidation request reception is possible by simply registering this holding position in the column memory, and the tag is Since there is no need to access the memory for invalidation execution, there are more opportunities to accept access requests to the cache buffer, and the performance of the data processing device can be improved.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the invention, FIG. 2 shows details of this embodiment, and FIG. 3 shows another embodiment of the invention. 1...Switching circuit, loo...Group 1st switching circuit, 110...2nd switching circuit, 2...Tag memo 1c 200...No. 1 tag memo l 21
0. Old... 2nd tag memo 1c 3... Comparison circuit, 300... Mark - 1st comparison circuit, 31O... 2nd comparison circuit, 4,400... Song replacement column designated circuit,
5,500... Song column memory, 6,600...
... Cache control circuit, 7,700 ... Tag memory control circuit, 8 ... Cache buffer '7
s 9..."Main memory, 11...Switcher, 12-Old...Register, 21+51...Random access memo 'i31+32.33+ 34-Comparator, 35I52+53+54t55+56+5
7+58+59*5A+5B+50+51-)+5g+
5F+61!62+63+64+65>66t67...
...Gate, A.Old...Access address, B...
... Invalidation request address, C ... Reset signal, Doooo ... First block address, E ... Group second block address, Fl ... Hit signal s F2 +F21. F22...Hit column information, G...
・Miss-hit signal, H...Access request, J.
... Replacement column information, K ... Invalidation request, L ... Contents held in column memory 5 5M ...
... Reset column information, P... group/group signal, Q.
...Inappropriate air signal. 25- A＾1 Aζl Figure

Claims (1)

[Scope of Claims] A plurality of data processing devices sharing a main storage device are provided, and at least one of the data processing devices has a cache buffer that holds copies of a plurality of data blocks in the main storage device over at least one column per address. The cache buffer control device in the data processing system includes a cache buffer control device, in which block address information regarding a data block held by the cache buffer is placed in a position corresponding to a position determined by an address and a column of the cache buffer. When checking the block address information read from the tag memory and determining whether there is a hit or miss, a bit at a position corresponding to the hit position in the tag memory is set and held. Column memory, and the access request acceptance is a hit determination that, when the comparison circuit determines a hit, the content held in the column memory is read out based on the hit column and the read address to the tag memory at this time. A cache buffer control device comprising: a cache control circuit that makes the same judgment as the mishit judgment.