JPS5929443A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS5929443A JPS5929443A JP57140107A JP14010782A JPS5929443A JP S5929443 A JPS5929443 A JP S5929443A JP 57140107 A JP57140107 A JP 57140107A JP 14010782 A JP14010782 A JP 14010782A JP S5929443 A JPS5929443 A JP S5929443A
- Authority
- JP
- Japan
- Prior art keywords
- synthetic resin
- lead
- resin
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体素子を合成樹脂によシ封止成形する半
導体装置用リードフレームに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame for a semiconductor device in which a semiconductor element is sealed and molded using a synthetic resin.
第1図は従来の半導体装置用リードフレームを示す平面
図である。同図において、(1)は外枠、(2)は複数
本のリード線、(3)はこの複数本のリード線(2)を
連結する連結片、(4)は図示せぬ半導体素子を装着す
るダイボンド工程およびワイヤボンド工程をへたのち、
クロスハツチングで示すように封止成形される合成樹脂
部、(5)はこの合成樹脂部(4)の端面、(6)は前
記連結片(3)の端面、(刀は前記リード線(2)の端
面、(8)は前記合成樹脂部(4)の端面(5)、前記
連結片(3)の端面(6)および前記リード線(2)の
端面(71で囲まれた空間部分である。FIG. 1 is a plan view showing a conventional lead frame for a semiconductor device. In the figure, (1) is an outer frame, (2) is a plurality of lead wires, (3) is a connecting piece that connects the plurality of lead wires (2), and (4) is a semiconductor element (not shown). After completing the die bonding process and wire bonding process,
As shown by crosshatching, the synthetic resin part is sealed and molded, (5) is the end face of this synthetic resin part (4), (6) is the end face of the connecting piece (3), (the sword is the lead wire ( 2), and (8) is a space surrounded by the end surface (5) of the synthetic resin part (4), the end surface (6) of the connecting piece (3), and the end surface (71) of the lead wire (2). It is.
この構成による半導体装置用リードフレームでは図示せ
ぬ半導体素子を装着するダイボンド工程を行なったのち
、樹脂封止成形工程を行なう。In a lead frame for a semiconductor device having this configuration, a die bonding process for mounting a semiconductor element (not shown) is performed, and then a resin sealing molding process is performed.
しかしながら、従来の半導体装置用リードフレームでは
樹脂封止成形工程において、合成樹脂が第2図に示すよ
うに空間部分(8)にも充填される。However, in the conventional lead frame for a semiconductor device, the space (8) is also filled with synthetic resin in the resin sealing molding process, as shown in FIG.
この空間部分(8)に充填されたリード樹脂(9)は樹
脂封止成形工程ののち、リード加工工程をへて、品質検
査ののち出荷されるまでには除去しなければならないが
、このリード間樹脂(9)を除去するには図示せぬリー
ド間樹脂除去装置(例えばプレス加工など)によっても
非常に困満Itであるうえ、パンチの破損および摩耗が
非常に多い。11斤に除去部品の先端形状を種々の複雑
かつ高価な形状にしているにもかかわらず、十分にリー
ドn月r7J脂<9)を除去することがで、きない現状
である。また、リード間樹脂(9)が半導体装置の一部
に付着した状態で、リード加工工程から最終検査工程が
行なわれると、このリード間樹脂(9)の悪影響によシ
\合成樹脂部(4)に割れ、欠け、傷あるいはリード線
(2)の変形などを起す。このように、生産性の低下お
よび歩留シを低下させるなどの欠点があった。The lead resin (9) filled in this space (8) must be removed after the resin sealing molding process, the lead processing process, and the quality inspection before being shipped. It is very difficult to remove the interlead resin (9) using an interlead resin removal device (for example, press processing, etc.) not shown, and the punch is often damaged and worn. Despite the fact that the tips of the parts to be removed are made into various complicated and expensive shapes, it is not possible to sufficiently remove lead n month r 7 J fat < 9). Furthermore, if the lead processing step to the final inspection step is performed with the inter-lead resin (9) adhering to a part of the semiconductor device, the synthetic resin part (4) may be damaged due to the adverse effects of the inter-lead resin (9). ) may cause cracks, chips, scratches, or deformation of the lead wire (2). As described above, there have been drawbacks such as a decrease in productivity and a decrease in yield.
したがって、この発明の目的はリード線の間のを間部分
に合成樹脂が充填されないようKすることができる半導
体装置用リードフレームを提供するものである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a lead frame for a semiconductor device that can prevent synthetic resin from being filled in the spaces between lead wires.
このような目的を達成するだめ、この発明はそれぞれの
リード線の間の空間部分に一端が入り込み、他端が連結
片に連結するダミー板を形成するものであり、以下実施
例を用いて詳細に説明する。In order to achieve such an object, the present invention forms a dummy plate having one end inserted into the space between the respective lead wires and the other end connected to the connecting piece. Explain.
第3図はこの発明に係る半導体装置用リードフレームの
一実施例を示す平面図である。同図において、(1ωは
前記リード線(2)間の空間部分をうめるように入り込
み、前記連結片(3)と一体をなすダミー板、0υはこ
のダミー板(10)とリード線(2)の端面(7)との
すき間、021はこのダミー板00)と合成樹脂部(4
)の端面(5)とのすき間である。FIG. 3 is a plan view showing an embodiment of a lead frame for a semiconductor device according to the present invention. In the figure, (1ω is a dummy plate that enters to fill the space between the lead wires (2) and is integrated with the connecting piece (3), and 0υ is the dummy plate (10) and the lead wire (2). The gap 021 between the end face (7) of the dummy plate 00) and the synthetic resin part (4
) and the end face (5).
この構成による半導体装置用リードフレームでは図示せ
ぬ半導体素子を装着するダイボンド工程。A die bonding process for mounting a semiconductor element (not shown) in a lead frame for a semiconductor device having this configuration.
そしてワイヤボンド工程を行なったのち、樹脂封止成形
工程を行なう。そして、この樹脂封止成形工程において
はダミー板0(I)により、クロスハツチングしだ合成
樹脂部(4)のみ樹脂封止成形される。After a wire bonding process is performed, a resin sealing molding process is performed. In this resin-sealing molding step, only the cross-hatched synthetic resin portion (4) is resin-sealed using the dummy plate 0 (I).
そして、図示せぬ連結切断装置によシ連結片(3)を切
断すると共にこのダミー板00)を切断する。Then, the connection piece (3) is cut by a connection cutting device (not shown), and the dummy plate 00) is also cut.
なお、上記実施例ではダミー板00)とリード線(2)
の端面(7)のすき間01)をリードフレームの板厚方
向に同一寸法としたが、第4図(a) K示すように勾
配を伺けてもよく、また第4図(b)K示すようにリー
ドフレームの板厚途中で段階を付けてもよいことはもち
ろんである。1だ、リード線(2)の長手方向における
すき間(11)も第5図に示すように段階を設けてもよ
いことはもちろんである。さらに、ダミー板00)と合
成樹脂(4)の端面(5)とのすき間([力についても
同様に勾配をつけてもよく、マた段階をつけてもよいこ
とはもちろんであ2゜
以上詳細に説明したように、この発明に係る半導体装置
用v −ト〕シレームによればリード間樹脂の除去装置
が全く不要になるプこめ、現有設備の転用が可能になる
と同時に新規設備費が一切不戦になる。また、リード間
樹脂の残りの有無を人手によ91個1個検査する作業が
全く無くなるため、工程の削減および人員の削減ができ
る。また、リード間(91脂の残シが原因する半導体装
置の外観不良が無くなシ、歩留シの向上、生産性の向上
が可能になる。しかも、リード間樹脂の除去が不要にな
り、かつリード間樹脂による悪影響が全くなくなるので
、封止工程の前工程、後工程との連結が可能になシ、生
産性の向上によシ、半導体装置のコスト低減になる。ま
た、リード間樹脂がないため、合成樹脂の消費量を削減
することができるなどの効果がある。In addition, in the above example, the dummy plate 00) and the lead wire (2)
The gap 01) on the end face (7) of the lead frame was made to have the same dimension in the thickness direction of the lead frame, but it may have a slope as shown in Figure 4 (a) K, or it may have a slope as shown in Figure 4 (b) K Of course, steps may be added in the middle of the thickness of the lead frame, as shown in FIG. 1. Of course, the gap (11) in the longitudinal direction of the lead wire (2) may also be provided in stages as shown in FIG. Furthermore, the gap between the dummy plate 00) and the end face (5) of the synthetic resin (4) ([For force, it goes without saying that a gradient may be applied in the same way, or a step may be applied; As explained in detail, according to the V-SIREM for semiconductor devices according to the present invention, a device for removing resin between leads is completely unnecessary, and existing equipment can be reused, and at the same time, there is no cost for new equipment. In addition, the work of manually inspecting each 91 piece for the presence or absence of residual resin between the leads is completely eliminated, reducing the number of processes and manpower. This eliminates defects in the appearance of semiconductor devices caused by lead-to-lead defects, improves yield, and improves productivity.Furthermore, there is no need to remove the resin between the leads, and the negative effects of the resin between the leads are completely eliminated. , it is possible to connect the pre-process and post-process of the sealing process, which improves productivity and reduces the cost of semiconductor devices.In addition, since there is no resin between the leads, the consumption of synthetic resin can be reduced. It has the effect of reducing
第1図は従来の半導体装置用リードフレームを示す平面
図、第2図は第1図に示す半導体装置用リードフレーム
に樹脂封止成形をした状態を示す平面図、第3図はこの
発明に係る半導体装置用リードフレームの一実施例を示
す平面図、第4図(、)および第4し1(b)はそれぞ
れダミー板とIJ−1,’純の端面のすき間の形状の他
の例を示す図、第5図はダミー板と合成樹脂の端面との
すき間の形状の他の例を示す図である。
(])・ ・・・外枠、(2)・・・ ・リード線、(
3)・・・・連結片、(4)・・・・合成樹脂部、(5
)、(6)および(7)・・・・端面、(8)・・・・
空間部分、(9)・・・・リード間il☆1脂、θ+l
)・・・・ダミー板、(+11および0々・・・・すき
間。
なお、図中、同−符一号は同一1だQよ相当部分を示す
。
代理人 葛 釣 信 −
第4図
(”) (b)
第5図
0
199−FIG. 1 is a plan view showing a conventional lead frame for a semiconductor device, FIG. 2 is a plan view showing a state in which the lead frame for a semiconductor device shown in FIG. 1 is molded with resin, and FIG. Plan views showing one embodiment of such a lead frame for a semiconductor device, FIGS. 4(a) and 4(a) and 1(b) respectively show other examples of the shape of the gap between the dummy plate and the end face of the IJ-1. FIG. 5 is a diagram showing another example of the shape of the gap between the dummy plate and the end face of the synthetic resin. (])...Outer frame, (2)... -Lead wire, (
3)...Connecting piece, (4)...Synthetic resin part, (5
), (6) and (7)... end face, (8)...
Space part, (9)... between leads il☆1 fat, θ+l
)... Dummy board, (+11 and 0 etc.... gaps. In the figure, the same - numerals and numbers indicate the same parts as the same 1 and Q. Agent Tsuri Nobu Kuzu - Figure 4 ( ”) (b) Figure 5 0 199-
Claims (1)
止成形する半導体装置用リードフレームにおいて、それ
ぞれのリード線の間の空間部分に一端が入シ込み、他端
が連結片に連結するダミー板を形成することを特徴とす
る半導体装置用IJ −ドフレーム。In lead frames for semiconductor devices that are sealed and molded with synthetic resin after a semiconductor element is attached to the sealing part, one end is inserted into the space between each lead wire, and the other end is connected to the connecting piece. 1. An IJ-doped frame for a semiconductor device, characterized in that a dummy plate is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57140107A JPS5929443A (en) | 1982-08-10 | 1982-08-10 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57140107A JPS5929443A (en) | 1982-08-10 | 1982-08-10 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5929443A true JPS5929443A (en) | 1984-02-16 |
Family
ID=15261092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57140107A Pending JPS5929443A (en) | 1982-08-10 | 1982-08-10 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5929443A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6169840U (en) * | 1984-10-11 | 1986-05-13 | ||
| JPS62168654U (en) * | 1986-04-16 | 1987-10-26 | ||
| JPS63164251A (en) * | 1986-12-26 | 1988-07-07 | Hitachi Ltd | Lead frame |
| FR2612448A1 (en) * | 1987-10-01 | 1988-09-23 | Asm Fico | Conductor frame for the flashless moulding of embedded metal elements, and method relating thereto |
-
1982
- 1982-08-10 JP JP57140107A patent/JPS5929443A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6169840U (en) * | 1984-10-11 | 1986-05-13 | ||
| JPS62168654U (en) * | 1986-04-16 | 1987-10-26 | ||
| JPS63164251A (en) * | 1986-12-26 | 1988-07-07 | Hitachi Ltd | Lead frame |
| FR2612448A1 (en) * | 1987-10-01 | 1988-09-23 | Asm Fico | Conductor frame for the flashless moulding of embedded metal elements, and method relating thereto |
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