JPS5929844U - matrix circuit - Google Patents
matrix circuitInfo
- Publication number
- JPS5929844U JPS5929844U JP12559282U JP12559282U JPS5929844U JP S5929844 U JPS5929844 U JP S5929844U JP 12559282 U JP12559282 U JP 12559282U JP 12559282 U JP12559282 U JP 12559282U JP S5929844 U JPS5929844 U JP S5929844U
- Authority
- JP
- Japan
- Prior art keywords
- power source
- movable contact
- transistors
- high potential
- potential end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims description 5
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Television Receiver Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のマトリックス回路の一例の回路図、第２
図は従来のマトリックス回路の他の例の回路図、第３図
は本考案の一実施例の回路図である。
１・・・・・・高電位端、２・・・・・・低電位端、３
．４・・・・・・入力端、５，６・・・・・・出力端、
７．８・・・・・・バッファ増幅器、９〜１５・・・・
・・抵抗、１７〜２０・・・・・・トランジスタ、２１
．２２・・・・・・スイッチ、２３・・・・・・バイア
ス’を源、２４． ２５−−−−−−トランジスタ、２
６゜２７・・・・・・抵抗。Figure 1 is a circuit diagram of an example of a conventional matrix circuit, and Figure 2 is a circuit diagram of an example of a conventional matrix circuit.
This figure is a circuit diagram of another example of a conventional matrix circuit, and FIG. 3 is a circuit diagram of one embodiment of the present invention. 1...High potential end, 2...Low potential end, 3
．． 4...Input end, 5,6...Output end,
7.8...Buffer amplifier, 9-15...
...Resistance, 17-20...Transistor, 21
．． 22...Switch, 23...Bias' source, 24. 25------transistor, 2
6゜27...Resistance.
Claims (1)
る２個のバッファ増幅器と、該バッファ増幅器の各々の
出力端にベースが接続しエミッタが当該バッファ増幅器
の反転入力端子に接続しコレクタが電源の高電位端に接
続する第１のトランジスタと、ベースが該第１のトラン
ジスタのベースと共通に前記バッファ増幅器の出力端に
接続する第２及び第３のトランジスタとから成る三つの
トランジスタを１組とする６個のトランジスタ群と、前
記トランジスタの各々のエミッタと前記電源の低電位端
との間に接続され実質的に同等の抵抗値を有する６個の
抵抗と、２個の連動する可動接点と３個の固定接点とを
１個のスイッチ内に有し一方の可動接点が前記電源の高
電位端に接続し他方の可動接点が負荷抵抗を介して前記
電源の高電位端に接続し一つの固定接点が前記の一方の
組の第２トランジスタのコレクタに接続し残りの固定接
点が共通接続して前記の他方の第３トランジスタのコレ
クタに接続する２つのスイッチと、前記バッファ増幅器
の非反転入力端子のそれぞれに抵抗を介してバイアスを
印加するバイアス電源と、前記負荷抵抗と前記スイッチ
の他方の可動接点とのそれぞれ接続点から引出される二
つの出力端子とを含むことを特徴とするマトリックス回
路。Two buffer amplifiers input different input signals to their respective non-inverting input terminals, the bases are connected to the output terminals of each of the buffer amplifiers, the emitters are connected to the inverting input terminals of the buffer amplifiers, and the collectors are connected to the power supply. A set of three transistors includes a first transistor connected to a high potential terminal, and second and third transistors whose bases are common to the base of the first transistor and connected to the output terminal of the buffer amplifier. six resistors connected between the emitters of each of the transistors and a low potential end of the power source and having substantially equal resistance values; and two interlocking movable contacts. One switch has three fixed contacts, one movable contact is connected to the high potential end of the power source, the other movable contact is connected to the high potential end of the power source via a load resistor, and one movable contact is connected to the high potential end of the power source through a load resistor. two switches whose fixed contacts are connected to the collectors of the second transistors of said one set and whose remaining fixed contacts are commonly connected to the collectors of said other third transistor; and a non-inverting input of said buffer amplifier. A matrix circuit comprising: a bias power supply that applies a bias to each of the terminals via a resistor; and two output terminals drawn out from respective connection points between the load resistor and the other movable contact of the switch. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12559282U JPS5929844U (en) | 1982-08-19 | 1982-08-19 | matrix circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12559282U JPS5929844U (en) | 1982-08-19 | 1982-08-19 | matrix circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5929844U true JPS5929844U (en) | 1984-02-24 |
| JPH0528825Y2 JPH0528825Y2 (en) | 1993-07-23 |
Family
ID=30285872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12559282U Granted JPS5929844U (en) | 1982-08-19 | 1982-08-19 | matrix circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5929844U (en) |
-
1982
- 1982-08-19 JP JP12559282U patent/JPS5929844U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0528825Y2 (en) | 1993-07-23 |
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