JPS5934652A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS5934652A
JPS5934652A JP57144931A JP14493182A JPS5934652A JP S5934652 A JPS5934652 A JP S5934652A JP 57144931 A JP57144931 A JP 57144931A JP 14493182 A JP14493182 A JP 14493182A JP S5934652 A JPS5934652 A JP S5934652A
Authority
JP
Japan
Prior art keywords
film
substrate
thin
thin film
large number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57144931A
Other languages
Japanese (ja)
Other versions
JPH0138376B2 (en
Inventor
Yoshiharu Nakao
中尾 ▲よし▼治
Masao Nagatomo
長友 正男
Yoshikazu Obayashi
大林 由和
Shinichi Sato
真一 佐藤
Kazuo Mizuguchi
一男 水口
Masahiro Yoneda
昌弘 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57144931A priority Critical patent/JPS5934652A/en
Publication of JPS5934652A publication Critical patent/JPS5934652A/en
Publication of JPH0138376B2 publication Critical patent/JPH0138376B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Landscapes

  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To form extremely fine and extremely shallow irregular sections, and to increase the area of an electrode by etching a substrate fitted to the IC while using a thin-film formed in a large number of insular structure as a mask when the irregular surface sections are formed to the substrate. CONSTITUTION:The silicon substrate 1 is oxidized to form a thermal oxide film 2 in several hundred Angstrom , and polysilicon films 3 formed in a large number of insular structure because they are extremely thin are grown. When the film 2 is etched while using the films 3 as masks and the films 3 are removed, the fine and extremely shallow irregular sections, the width and depth of grooves thereof are several hundred - several thousand Angstrom , can be formed to the substrate 1. A thin uniform thickness thermal oxide film 4 is formed to the surface of the substrate 1, and a polysilicon film 5 is deposited, thus obtaining a capacitor, which uses the substrate 1 and the film 5 as electrodes and capacitance per unit projected area thereof increases.

Description

【発明の詳細な説明】 本発明は、単位投影面積当りの静電容量を増加させるた
めになされ、ICに適合した基板に凹凸をつける方法に
関するものでちる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for increasing capacitance per unit projected area and for forming irregularities on a substrate suitable for an IC.

従来、単位投影面積当りの静電容量を増加するために電
極に凹凸をつける方法は、電解コンデンサ等で実用され
ている。この方法は、例えば、アルミニウム電解コンデ
ンサの場合、アルミニウム電極を塩酸等によって表面を
腐食させ、結果として、電子顕微鏡レベルまで拡大しで
も、スポンジ状に見える凹凸をつけ、しかる後、コンデ
ンザ用の陽極酸化膜を形成し、一方の電極はもちろん、
上記のアルミニウム電極とし、他の一方の電極は、液体
酸の場合は電解液とし、固体型のよ(3合は例えばマン
ガン酸化物として、小型で大容量の電解コンデンサを実
現している。
Conventionally, a method of forming irregularities on electrodes in order to increase capacitance per unit projected area has been put to practical use in electrolytic capacitors and the like. For example, in the case of an aluminum electrolytic capacitor, this method corrodes the surface of the aluminum electrode with hydrochloric acid, etc., resulting in unevenness that looks spongy even when magnified to the level of an electron microscope. Forming a film, one electrode is of course
The above-mentioned aluminum electrode is used, and the other electrode is an electrolyte in the case of a liquid acid, and a solid type (for example, manganese oxide in the case of a solid type) to realize a small and large-capacity electrolytic capacitor.

このような技術をICのコンデンサの製造に適用すると
、ICの製造工程で薬品にさらしたのち高温炉に投入す
ることはよくあるが、上記の如き、スポンジ状の電極構
造ではスポンジ状の四部に残存する薬品類が上記の炉を
汚染する欠点があった。
When this kind of technology is applied to the manufacture of IC capacitors, the IC is often exposed to chemicals in the manufacturing process and then put into a high-temperature furnace. There is a drawback that the remaining chemicals contaminate the above-mentioned furnace.

その他に、スポンジ状の穴に残存する薬品が完成品の信
頼性を低下させたり、また折角、凹凸をつけ面積を稼い
でも、対向電極材料に選択の余地がなく、その面積の極
く一部しか利用できないなどの欠点かあった。
In addition, chemicals remaining in the sponge-like holes reduce the reliability of the finished product, and even if you take the pains to create unevenness to increase the area, there is no choice in the counter electrode material, and only a small portion of that area There were drawbacks such as the fact that it could only be used in

また、従来の写真食刻法を用いても凹凸をつけることは
可能であるが、凹凸の繰シ返しの寸法は、写真食7jj
 O)最小寸法より小さくできないことより、以下の二
つの欠点が生じる。すなわち、凹凸によって面積を塔加
さセる場合、穴の幅に対してその深さは、同程夏かさら
に大きくないと、面例な工程を採用するのに見合った面
積増加は望めない。
Furthermore, although it is possible to create unevenness using the conventional photoetching method, the dimensions of the repeated unevenness are limited by photoetching.
O) The following two drawbacks occur because the size cannot be made smaller than the minimum size. In other words, if the area is increased by using unevenness, unless the depth is about the same or even larger than the width of the hole, it will not be possible to expect an increase in area commensurate with the adoption of a standard process.

穴の幅は現在の実用レベルの最小値で約2μmであるか
ら、探さは2μm以上となる。このような深い凹凸上に
、後工程で電極栃料に2μmはどと百っだ微細なパター
ン形成かできないことが第1の欠点であり、もう一つの
欠点は、IC中のコンデンサの#E横のサイズか上記の
写X食刻の最小寸法とほぼ同じ大きさとなり事実上適用
できないことであった。
Since the width of the hole is about 2 μm at the current practical level minimum width, the width of the hole is 2 μm or more. The first drawback is that it is only possible to form a pattern as fine as 2 μm on the electrode material in the subsequent process on such deep unevenness, and the other drawback is that #E of the capacitor in the IC The horizontal size was almost the same as the minimum dimension of the above-mentioned photo-X engraving, making it virtually impossible to apply.

本発明は、上記の如き従来のものの欠点を除去するため
になされたもので、非常に薄いために多数の島状構造に
形成された薄膜をマスクにして食刻することによシ、基
板に形状・寸法は不規則であるが、極めて微細で極めて
浅い凹凸を形成し充分な電極面積の増加をもたらす方法
を提供することを目的としている。
The present invention was made in order to eliminate the drawbacks of the conventional methods as described above. Although the shape and dimensions are irregular, the object is to provide a method of forming extremely fine and extremely shallow irregularities to sufficiently increase the electrode area.

以下、本発明の一実施例を図面によって説明する。第1
図〜第4図は本発明の一実施例の主要工程における状態
を示す断面図である。
An embodiment of the present invention will be described below with reference to the drawings. 1st
4 to 4 are cross-sectional views showing the main steps of an embodiment of the present invention.

第1図はシリコン基板[11を酸化し数100 Aの熱
酸化膜(2)を形成し、さらに非常に薄いために多数の
島状構造に形成されるポリシリコン膜(3)を成長させ
たものである。このポリシリコ/膜(3)の島状構造の
粒径は、膜厚、成長温度等で制御でき、数100〜数1
000 Aの範囲にすることは可能である。
Figure 1 shows that a silicon substrate [11] was oxidized to form a thermal oxide film (2) of several hundred amperes, and then a polysilicon film (3), which was extremely thin and formed into many island-like structures, was grown. It is something. The particle size of the island-like structure of this polysilico/film (3) can be controlled by the film thickness, growth temperature, etc.
A range of 000 A is possible.

第2図はポリシリコン膜(3)をマスクに熱酸化膜(2
)をエツチングした状態を示す。このとき、実際には、
後の電極面積増加が最大になるように、ポリシリコン膜
(3)の下の熱液化膜(2)に、適当なアンダー・カッ
ティング(undercutting)を行い、この熱
酸化膜(2)の抜き残しの比を制御することはいうまで
もない。
Figure 2 shows a thermal oxide film (2) using a polysilicon film (3) as a mask.
) is shown after being etched. At this time, actually
Appropriate undercutting is performed on the thermally liquefied film (2) under the polysilicon film (3) to maximize the subsequent increase in electrode area, and this thermally oxidized film (2) is removed. Needless to say, it is necessary to control the ratio.

第3図は第2図の熱酸化膜(2)をマスクにしてシリコ
ン基板f1)を数100〜数1000Aエツチングした
状態を示す。このとき、いわゆる異方性エツチングを行
うのが面積増加を図る上で有利で、その場合には、前も
って、第2図におけるポリシリコン膜(3)のヒサシ部
分〔熱酸化膜(2)のアンダー・カットのある場合〕を
等方性エツチングにより除去するのが望ましい。
FIG. 3 shows a state in which the silicon substrate f1) has been etched by several hundred to several thousand amps using the thermal oxide film (2) of FIG. 2 as a mask. At this time, it is advantageous to perform so-called anisotropic etching in order to increase the area.・If there is a cut, it is desirable to remove it by isotropic etching.

第4図は第3図の熱酸化膜(3)を除去した状態を示し
、シリコン基板[1]に溝の幅・深さが数100〜数1
000人の微細かつ極めて浅い凹凸をつけることができ
ることを示している。
Figure 4 shows a state in which the thermal oxide film (3) in Figure 3 has been removed, and the width and depth of the grooves in the silicon substrate [1] ranges from several hundred to several tens.
This shows that it is possible to create fine and extremely shallow irregularities of 1,000 people.

第5図は、第4図に示すような極めて微細な凹凸のつい
たシリコン基板i1)の表面に薄い一様な厚さの熱酸化
膜(4)を形成したのち、ポリシリコン膜(5)を堆積
させることにより、シリコン基板(1)とポリシリコン
膜(5)とを電極とし単位投影面積当りの容量が増加し
たコンデンサを得ることを示した図である。
Figure 5 shows that after forming a thin thermal oxide film (4) of uniform thickness on the surface of a silicon substrate i1) with extremely fine irregularities as shown in Figure 4, a polysilicon film (5) is formed. FIG. 3 is a diagram showing that a capacitor with increased capacitance per unit projected area is obtained by using a silicon substrate (1) and a polysilicon film (5) as electrodes.

以上の説明では、簡単なため省略したが、実際のICで
は、以十の如き工程を経るのが普通である。すなわち、
凹凸を付ける必要のない部分には、例えば第1図の状態
のときに、写真製版法で7オトーレジストで覆う工程を
入れることや、また、シリコン基板fi+の表面にこの
シリコン基板[11と同じ伝導型または反対の伝導型の
拡散層、エピタキシャル層等を第4図の状態のとき、ま
たは第1図の熱酸化膜(2)を付着させる前に、形成す
る工程を入れることや、第5図のポリシリコン膜(5)
に不純物を拡散しシート抵抗を低下させる工程を入れる
こと等はいうまでもない。
In the above explanation, the process has been omitted for simplicity, but in an actual IC, the following ten steps are normally performed. That is,
For areas where there is no need to create unevenness, for example, in the state shown in Figure 1, a step of covering with a photoresist may be added to the surface of the silicon substrate fi+. A step of forming a diffusion layer, an epitaxial layer, etc. of the conductivity type or the opposite conductivity type in the state shown in FIG. 4 or before depositing the thermal oxide film (2) in FIG. Polysilicon film (5) in the figure
Needless to say, a step is included to diffuse impurities into the film to lower the sheet resistance.

以上は基板と同じ材質の薄い島状構造の薄膜をマスクと
する場合について述べたが、異なる材質、例えば金、ア
ルミニウム等の金属や、他の半導体材料、絶縁材料等を
用いても同様のことが実現できることはいうまでもない
。また、島状構造の薄膜の形状を写しとるための膜とし
ては熱酸化膜以外にも、数100A程度の薄さでも一様
な厚みを保証するものでシリコンに対してマスク効果の
ある。
The above describes the case where a thin island-shaped thin film made of the same material as the substrate is used as a mask, but the same effect can be obtained using a different material, such as metals such as gold and aluminum, other semiconductor materials, insulating materials, etc. It goes without saying that this can be achieved. Further, as a film for copying the shape of a thin film having an island-like structure, other than a thermal oxide film, there is a film that guarantees a uniform thickness even if it is as thin as several hundred amps, and has a masking effect on silicon.

ものであれば良く、例えば熱窒化膜であってもよい。For example, it may be a thermal nitride film.

また、上記の島状構造の薄膜が、シリコンに対してマス
クとなる材質の場合、島状構造の薄膜をシリコン基板に
直接に付着させ、そのままシリコン基板をエツチングす
ることでも、ごの方法によっても、はぼ第4図の構造を
実現できる。しかし、この場合には、実施例で述べたア
ンダー・カッティングにより抜き残しの比率を制御する
ことができないので、効率の良い面積増加は望めない。
In addition, if the above-mentioned thin film with an island-like structure is made of a material that acts as a mask for silicon, the thin film with an island-like structure can be directly attached to the silicon substrate and the silicon substrate can be etched as is. , the structure shown in FIG. 4 can be realized. However, in this case, it is not possible to control the ratio of uncut parts due to the undercutting described in the embodiment, so it is not possible to efficiently increase the area.

以上のように、本発明によればマスクに島状構造の薄膜
を利用するので、不規則ではあるが平均的な凹部の幅間
隔を数100〜数100OAといった短い長さにするこ
とができ、凹部の深さも数100〜数1000 A程度
であるから、凹凸による充分な面積増加を図ることがで
きる効果がある。
As described above, according to the present invention, since a thin film with an island-like structure is used in the mask, the average width interval of the recesses can be made short, although irregular, such as several 100 to several 100 OA. Since the depth of the recessed portion is also approximately several hundred to several thousand amps, there is an effect that the area can be sufficiently increased due to the unevenness.

【図面の簡単な説明】[Brief explanation of the drawing]

第1〜第4図は本発明の一実施例の主要工程を示す断面
図、第5図は本発明の方法を用いたコンデンサの断面図
である。 図において、(1)はシリコン基板、(2)は熱酸化膜
、(3)は島状構造のポリシリコン膜、(4)は熱酸化
膜、(5)はポリシリコン膜である。 なお、図中同一符号はそれぞれ同一または相当部分を示
す。 代理人  葛 野 信 −(外1名)
1 to 4 are cross-sectional views showing the main steps of an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a capacitor using the method of the present invention. In the figure, (1) is a silicon substrate, (2) is a thermal oxide film, (3) is a polysilicon film with an island-like structure, (4) is a thermal oxide film, and (5) is a polysilicon film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno - (1 other person)

Claims (1)

【特許請求の範囲】 fil  多数の微細な島状構造を形成する程度に薄い
薄膜を基板上に付着させる工程、および島状構造の上記
薄膜をマスクにして上記基板を食刻しその表面部に多数
の微細な凹凸を形成する工程を備えたことを特徴とする
半導体集積回路装置の製造方法。 (2)基板上にほぼ一様な厚さの第1の薄膜を形成する
工程、多数の微細な島状構造を形成する程度に薄い第2
の薄膜を上記第1の薄膜の表面上に付着させる工程、島
状構造の上記第2の薄膜をマスクにして上記第1の薄膜
を食刻し多数の微細な開口部を形成する工程、および上
記開口部が形成された上記第1の薄膜をマスタにして上
記基板を食刻しその表面部に多数の微細な凹凸を形成す
る工程を備えたことを特徴とする半導体集積回路装置の
製造方法。
[Claims] fil A step of depositing a thin film thin enough to form a large number of fine island-like structures on a substrate, and etching the substrate using the thin film of the island-like structure as a mask to form a surface portion of the thin film. A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a large number of fine irregularities. (2) A step of forming a first thin film with a substantially uniform thickness on a substrate, and a second film thin enough to form a large number of fine island-like structures.
a step of depositing a thin film on the surface of the first thin film; a step of etching the first thin film using the second thin film having an island-like structure as a mask to form a large number of fine openings; A method for manufacturing a semiconductor integrated circuit device, comprising the step of etching the substrate using the first thin film in which the opening is formed as a master to form a large number of fine irregularities on the surface thereof. .
JP57144931A 1982-08-20 1982-08-20 Manufacture of semiconductor integrated circuit device Granted JPS5934652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57144931A JPS5934652A (en) 1982-08-20 1982-08-20 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57144931A JPS5934652A (en) 1982-08-20 1982-08-20 Manufacture of semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5934652A true JPS5934652A (en) 1984-02-25
JPH0138376B2 JPH0138376B2 (en) 1989-08-14

Family

ID=15373527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57144931A Granted JPS5934652A (en) 1982-08-20 1982-08-20 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5934652A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100588737B1 (en) 2004-12-30 2006-06-12 매그나칩 반도체 유한회사 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100588737B1 (en) 2004-12-30 2006-06-12 매그나칩 반도체 유한회사 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0138376B2 (en) 1989-08-14

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