JPS593565U - Wiring structure of multilayer printed board - Google Patents

Wiring structure of multilayer printed board

Info

Publication number
JPS593565U
JPS593565U JP9830882U JP9830882U JPS593565U JP S593565 U JPS593565 U JP S593565U JP 9830882 U JP9830882 U JP 9830882U JP 9830882 U JP9830882 U JP 9830882U JP S593565 U JPS593565 U JP S593565U
Authority
JP
Japan
Prior art keywords
printed board
holes
multilayer printed
wiring structure
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9830882U
Other languages
Japanese (ja)
Inventor
西原 幹雄
敏弘 草谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9830882U priority Critical patent/JPS593565U/en
Publication of JPS593565U publication Critical patent/JPS593565U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案に係る多層プリント板の配線構造の実施例
を示すもので、第1図は信号層のパターン配置図、第2
図は配線パターン形成方向説明図、第3図は各方向パタ
ーンと中継ホール設置可能位置の関係説明図である。 図中、1はスルーホール、2は配線パターンである。
The drawings show an embodiment of the wiring structure of a multilayer printed board according to the present invention.
The figure is an explanatory diagram of wiring pattern formation directions, and FIG. 3 is an explanatory diagram of the relationship between patterns in each direction and positions where relay holes can be installed. In the figure, 1 is a through hole and 2 is a wiring pattern.

Claims (1)

【実用新案登録請求の範囲】 複数層の信号層を積層してなり搭載部品の端子を接続す
るスルーホールを備えた多層プリント板において、前記
スルーホールをX方向に対し千鳥状に配設するとともに
、前記各信号層の前記各スルーホールおよび該各スルー
ホール間を2等分する位置を通りX方向に対しそれぞれ
0°、45°、。 90°、135°傾斜する4方向の配線パターンを形成
し、該配線パターンの前記スルーホールを除く交点のす
べてに層間接続用の微小ホールが設置できるように構成
したことを特徴とする多層プリント板の配線構造。
[Claims for Utility Model Registration] A multilayer printed board made of a plurality of layered signal layers and provided with through holes for connecting terminals of mounted components, wherein the through holes are arranged in a staggered manner in the X direction, and , 0° and 45°, respectively, with respect to the X direction passing through each of the through holes of each of the signal layers and a position that bisects the space between the through holes. A multilayer printed board, characterized in that a wiring pattern is formed in four directions inclined at 90° and 135°, and is configured such that micro holes for interlayer connection can be installed at all intersections of the wiring pattern except for the through hole. wiring structure.
JP9830882U 1982-06-30 1982-06-30 Wiring structure of multilayer printed board Pending JPS593565U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9830882U JPS593565U (en) 1982-06-30 1982-06-30 Wiring structure of multilayer printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9830882U JPS593565U (en) 1982-06-30 1982-06-30 Wiring structure of multilayer printed board

Publications (1)

Publication Number Publication Date
JPS593565U true JPS593565U (en) 1984-01-11

Family

ID=30233472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9830882U Pending JPS593565U (en) 1982-06-30 1982-06-30 Wiring structure of multilayer printed board

Country Status (1)

Country Link
JP (1) JPS593565U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5530822A (en) * 1978-08-25 1980-03-04 Fujitsu Ltd Printed board
JPS562271B2 (en) * 1976-08-13 1981-01-19
JPS5612179B2 (en) * 1975-10-11 1981-03-19

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612179B2 (en) * 1975-10-11 1981-03-19
JPS562271B2 (en) * 1976-08-13 1981-01-19
JPS5530822A (en) * 1978-08-25 1980-03-04 Fujitsu Ltd Printed board

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