JPS5936633U - Analog VFO frequency memory circuit - Google Patents

Analog VFO frequency memory circuit

Info

Publication number
JPS5936633U
JPS5936633U JP3854083U JP3854083U JPS5936633U JP S5936633 U JPS5936633 U JP S5936633U JP 3854083 U JP3854083 U JP 3854083U JP 3854083 U JP3854083 U JP 3854083U JP S5936633 U JPS5936633 U JP S5936633U
Authority
JP
Japan
Prior art keywords
frequency
counter
memory circuit
programmable
bcd code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3854083U
Other languages
Japanese (ja)
Inventor
伸郎 小川
Original Assignee
八重洲無線株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 八重洲無線株式会社 filed Critical 八重洲無線株式会社
Priority to JP3854083U priority Critical patent/JPS5936633U/en
Publication of JPS5936633U publication Critical patent/JPS5936633U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は、本考案の実施例を示すブロック
図である。 １・・・ＶＦｏ、　２・・・ｖｃｏ、３・・・プログラ
マブル分周器、４・・・位相検波器、５・・・基準周波
数発振器、６・・・ＬＰＦ、７・・・ゲート、８・・・
周波数カウンタ、９・・・ラッチ、１０・・・メモリス
イッチ、１１・・・出力Ｍスイッチ、１２・・・和／差
カウンタ。1 and 2 are block diagrams showing an embodiment of the present invention. 1...VFo, 2...vco, 3...programmable frequency divider, 4...phase detector, 5...reference frequency oscillator, 6...LPF, 7...gate, 8 ...
Frequency counter, 9...Latch, 10...Memory switch, 11...Output M switch, 12...Sum/difference counter.

Claims (1)

【実用新案登録請求の範囲】 ■　少なくと′も次の各項より構成され、アナログＶＦ
Ｏの発生する任意の周波数を記憶して、必要に応じて再
現し得ることを特徴とするアナログＶＦＯの周波数メモ
リ回路。　　　′（１）ＶＣＯ、プログラマブル分周器
、基準周波数発振器、位相検波器およびＬＰＦよりなる
ＰＬＬ発振回路。 （２）前記基準周波数によりゲート時間を設定して、Ｖ
ＦＯの周波数を計測してＢＣＤコードを出力し、前記プ
ログラマブル分周器の分周比を制御する周波数カウンタ
。 （３）前記周波数カウンタとプログラマブル分周器との
間に挿入してＢＣＤコードを保持するラッチ。 ■　少なくも次の各項より構成されることを特徴とする
実用新案登録請求の範囲第１項に記載のアナログＶＦＯ
の周波数メモリ回路。 （１）　　ＶＦＯ，プログラマブル分周器、該分周器の
分周比を設定する和／差カウンタ、基準周波数発振器、
位相検波器およびＬＰＦよりなるＰＬＬ発振回路。 （２）前記基準周波数によりゲート時間を設定して、Ｖ
ＦＯの周波数を計測してＢＣＤコードを出力し、前記Ｐ
ＬＬ発振回路の和／差カウンタに供給する　　　−周波
数カウンタ。 （３）前記周波数カウンタと和／差カウンタとの間に挿
入してＢＣＤコードを保持するラッチ。[Claims for Utility Model Registration] ■ At least '' also consists of the following items, and
A frequency memory circuit for an analog VFO, characterized in that an arbitrary frequency generated by O is memorized and can be reproduced as needed. '(1) A PLL oscillation circuit consisting of a VCO, a programmable frequency divider, a reference frequency oscillator, a phase detector, and an LPF. (2) Set the gate time according to the reference frequency and
A frequency counter that measures the frequency of the FO, outputs a BCD code, and controls the frequency division ratio of the programmable frequency divider. (3) A latch inserted between the frequency counter and the programmable frequency divider to hold the BCD code. ■ An analog VFO according to claim 1 of the utility model registration claim, which is comprised of at least the following items:
frequency memory circuit. (1) VFO, programmable frequency divider, sum/difference counter that sets the division ratio of the frequency divider, reference frequency oscillator,
PLL oscillation circuit consisting of a phase detector and LPF. (2) Set the gate time according to the reference frequency and
Measure the frequency of FO, output the BCD code, and
- Frequency counter that supplies the sum/difference counter of the LL oscillation circuit. (3) A latch inserted between the frequency counter and the sum/difference counter to hold the BCD code.
JP3854083U 1983-03-17 1983-03-17 Analog VFO frequency memory circuit Pending JPS5936633U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3854083U JPS5936633U (en) 1983-03-17 1983-03-17 Analog VFO frequency memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3854083U JPS5936633U (en) 1983-03-17 1983-03-17 Analog VFO frequency memory circuit

Publications (1)

Publication Number Publication Date
JPS5936633U true JPS5936633U (en) 1984-03-07

Family

ID=30169204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3854083U Pending JPS5936633U (en) 1983-03-17 1983-03-17 Analog VFO frequency memory circuit

Country Status (1)

Country Link
JP (1) JPS5936633U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5261465A (en) * 1975-11-17 1977-05-20 Torio Kk Oscillating circuit
JPS5263607A (en) * 1975-11-20 1977-05-26 Alps Electric Co Ltd Transceiver with memory function
JPS5467749A (en) * 1977-11-10 1979-05-31 Yaesu Musen Kk Analog vfo frequency memory circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5261465A (en) * 1975-11-17 1977-05-20 Torio Kk Oscillating circuit
JPS5263607A (en) * 1975-11-20 1977-05-26 Alps Electric Co Ltd Transceiver with memory function
JPS5467749A (en) * 1977-11-10 1979-05-31 Yaesu Musen Kk Analog vfo frequency memory circuit

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