JPS594014A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS594014A
JPS594014A JP57113117A JP11311782A JPS594014A JP S594014 A JPS594014 A JP S594014A JP 57113117 A JP57113117 A JP 57113117A JP 11311782 A JP11311782 A JP 11311782A JP S594014 A JPS594014 A JP S594014A
Authority
JP
Japan
Prior art keywords
layer
wiring
region
diffusion layer
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57113117A
Other languages
Japanese (ja)
Inventor
Shigeo Kashiwagi
柏木 茂雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57113117A priority Critical patent/JPS594014A/en
Publication of JPS594014A publication Critical patent/JPS594014A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To avoid the increase of contact resistance by removing a natural oxide film formed onto a diffusion layer of the semiconductor device, attaching pure Al wiring to the natural oxide film and coating the upper section of the Al wiring with a wiring metallic layer, which contains Si and consists of Al, when metallic wiring is attached onto the diffusion layer. CONSTITUTION:An n<+> type region 24 is diffused and formed to a p type Si substrate 21, the region 24 is coated with a PSG film 22 with an opening corresponding to the region 24, and the region 24 exposed in the opening is coated with an amorphous Si layer 25. The pure Al layer 23 is sputtered to the whole surface at a temperature of 300-400 deg.C, and spikes 26 are grown in the region 24 through a reaction with the amorphous layer 25. The spikes 26 penetrate the Si layer 25 and intrude into the region 24 at that time, but they need not intrude into the substrate 21. The whole surface is coated with the Al layer 27 containing 1-2% Si, and the metallic wiring in which contact resistance does not increase is obtained.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は半導体装置の製造方法、詳しくは拡散層と配線
金属とのコンタクト部(接触部)における接触抵抗(コ
ンタクト抵抗)の増大防止方法に関する。
Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing an increase in contact resistance at a contact portion between a diffusion layer and a wiring metal. .

(2)技術の背景 半導体基板例えばシリコン基板に形成された拡散層と金
属配線(例えばアルミニウム)とのコ(1) ンタクト形成においては、コンタクト抵抗を低くおさえ
ることが重要である。拡散層は通品シリコン基板に不純
物注入を行なった後熱処理拡散をなして形成されるが、
この拡散層表面には一般に最高200人程度の厚さの自
然酸化膜(natural oxi−de)が形成され
、この酸化膜は電極コンタクトをとるにおいて高抵抗層
となるため、従来エツチングにより除去している。
(2) Background of the Technology In forming a contact between a diffusion layer formed on a semiconductor substrate, such as a silicon substrate, and a metal wiring (for example, aluminum) (1), it is important to keep the contact resistance low. The diffusion layer is formed by implanting impurities into a standard silicon substrate and then performing heat treatment diffusion.
A natural oxide film (natural oxide) with a maximum thickness of about 200 nm is generally formed on the surface of this diffusion layer, and since this oxide film becomes a high resistance layer when making electrode contact, it is conventionally removed by etching. There is.

しかしてエツチングは工程が簡単なアルゴン(Ar)プ
ラズマによる高周波(RF)エツチングを行なっている
が、この処理の結果、拡散層表面がアモルファス化(非
晶化)され高抵抗層が形成されることが確言忍されてい
る。
However, radio frequency (RF) etching using argon (Ar) plasma is used, which is a simple process, but as a result of this process, the surface of the diffusion layer becomes amorphous (non-crystalline) and a high resistance layer is formed. It is confirmed that it is being tolerated.

(3)従来技術と問題点 このアモルファス層は前記自然酸化膜よりは低抵抗であ
るが、半導体装置の動作特性に与える影響は無視できな
いものであることが確かめられ、なんらかの対応策が要
望されている。
(3) Prior art and problems Although this amorphous layer has a lower resistance than the above-mentioned natural oxide film, it has been confirmed that its influence on the operating characteristics of semiconductor devices cannot be ignored, and some countermeasures are desired. There is.

第1図は従来技術における拡散層と配線金属とのコンタ
クト形成方法を説明するための半導体(2) 装置要部の断面図で、同図を参照すると、例えばN膨拡
散層3が形成されたP形シリコン半導体基板1上に燐シ
リケートガラス(PSG )膜2を形成した後、コンタ
クト部分を窓開けし、次いでアルゴンプラズマによるR
Fエツチングでコンタクト前処理を行い拡散層表面の自
然酸化膜(図示せず)を除去する(同図(a))。
Figure 1 is a cross-sectional view of the main part of a semiconductor device (2) for explaining a method of forming a contact between a diffusion layer and a wiring metal in the prior art. After forming a phosphorus silicate glass (PSG) film 2 on a P-type silicon semiconductor substrate 1, a window is opened in the contact area, and then R is applied using argon plasma.
Contact pretreatment is performed using F etching to remove the natural oxide film (not shown) on the surface of the diffusion layer (FIG. 4(a)).

このとき拡散層3の表面の結晶性が乱されアモルファス
化することが確認された。このアモルファス化した部分
(同図(blに砂地4で示す)はコンタクト抵抗を大に
する欠点はあるが、前記自然酸化膜に比べれば低抵抗で
あり、またこのアモルファス化した部分を除去し低抵抗
化を計る技術が未だ開発されていないため、同図(C1
に示す如く、シリコン(Si)を1〜2%含むアルミニ
ウム(^7り配線5を直接付着してコンタクトをとる方
法が用いられている。なお上記i配線5はスパックリン
グもしくは蒸着によって厚さ1μmに付着され、また含
有されるシリコンは基板1からアルミニウム配線5への
シリコン原子の吸込みによ(3) ろ過度の合金化反応によって拡散層の接合を破壊してし
まうのを防止する目的をもつ。
At this time, it was confirmed that the crystallinity of the surface of the diffusion layer 3 was disturbed and it became amorphous. Although this amorphous part (shown as sandy area 4 in the figure (BL)) has the disadvantage of increasing the contact resistance, it has a lower resistance compared to the natural oxide film, and by removing this amorphous part, the contact resistance increases. Since the technology to measure resistance has not yet been developed, the same figure (C1
As shown in the figure, a method is used in which contact is made by directly attaching an aluminum wiring 5 containing 1 to 2% silicon (Si).The i wiring 5 is made to have a thickness of 1 μm by spattering or vapor deposition. The silicon attached to and contained in the aluminum wiring 5 is caused by the suction of silicon atoms from the substrate 1 into the aluminum wiring 5 (3).It has the purpose of preventing the bonding of the diffusion layer from being destroyed due to the alloying reaction during filtration. .

以上述べた如く、従来技術においてはコンタクト形成に
おける前処理の結果、拡18!層表面にアモルファス化
した部分が形成されコンタクト抵抗が高くなる問題は依
然として解決されていない。
As mentioned above, in the prior art, as a result of pre-treatment during contact formation, the expansion is 18! The problem of high contact resistance due to the formation of amorphous portions on the layer surface remains unsolved.

(4)発明の目的 本発明は上記従来の問題点に鑑み、コンタクト抵抗の増
大防止が可能な金属配線と拡散層とのコンタクト形成方
法の提供を目的とする。
(4) Purpose of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to provide a method for forming a contact between a metal wiring and a diffusion layer, which can prevent an increase in contact resistance.

(5)発明の構成 そしてこの目的は、本発明の方法によれば、前記前処理
の後、適宜選択された前処理温度の下で、適宜選定され
た厚さの純粋アルミニウム層を配線領域に付着し、当該
アルミニウムとシリコン基板との反応により、拡散層内
に上記アモルファス層を貫通ずるがしかし拡散層を突破
することのないアルミニウムの針状突起(スパイクと呼
ばれル)ヲ成長させ、次いで純粋i層上にシリコン含有
のi配線金属を形成し、これらスパイクを(4) もって拡散層と配線金属間のコンタクト抵抗の増大防止
を計ることを特徴とする半導体装置の製造方法を提供す
ることによっ゛ζ達成され、前記した前処理温度と純粋
へ1層の厚さは、上記のAlのスパイクがアモルファス
層をつきぬけて拡散層内に延びるが、拡散層をつきぬけ
°ζ基板バルクに達することのないように選定する。
(5) Structure of the invention and this object is that according to the method of the invention, after the pretreatment, a pure aluminum layer of a suitably selected thickness is applied to the wiring area under a suitably selected pretreatment temperature. The reaction between the aluminum and the silicon substrate causes the growth of aluminum needle-like projections (called spikes) in the diffusion layer that penetrate the amorphous layer but do not break through the diffusion layer. To provide a method for manufacturing a semiconductor device, characterized in that a silicon-containing i-wiring metal is formed on a pure i-layer, and these spikes (4) are used to prevent an increase in contact resistance between a diffusion layer and a wiring metal. The pretreatment temperature and pure single layer thickness achieved by ζ are such that the Al spikes described above extend through the amorphous layer and into the diffusion layer, but only when they penetrate through the diffusion layer and reach the bulk of the substrate. Make sure that there are no problems.

(6)発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明の詳細な説明するための半導体装置要部
の断面図で、同図を参照すると、まず従来技術と同様に
してRFエツチングによる前処理を行いアモルファス層
が拡散層表面に形成される工程(第1図ta+、(b)
)を行う。
FIG. 2 is a cross-sectional view of the main part of a semiconductor device for explaining the present invention in detail. Referring to the figure, first, as in the prior art, pretreatment by RF etching is performed to form an amorphous layer on the surface of the diffusion layer. (Fig. 1 ta+, (b)
)I do.

次いで、第2図(a)に示す如く、純粋アルミニウムJ
−23を300°C〜400°Cの温度の下でスパック
リングにより1000人未満の厚さに形成すると、アモ
ルファス層25との反応により拡散層24内にスパイク
26が成長する。なお同図において21は例えば1)形
シリコン基板、22はPSG 膜、25はアモルファ(
5) ス層を示す。
Next, as shown in FIG. 2(a), pure aluminum J
When -23 is formed to a thickness of less than 1,000 by spackling at a temperature of 300° C. to 400° C., spikes 26 grow in the diffusion layer 24 due to reaction with the amorphous layer 25. In the figure, 21 is, for example, a 1) type silicon substrate, 22 is a PSG film, and 25 is an amorphous (
5) Indicates the layer.

ところで上記スパイク26は、図示の如く基板21の表
面からアモルファス層25をつきぬけるが、拡散層24
を通りぬけ基板21のバルクには到達しないように形成
する。このようなスパイクの形成は純粋アルミニウム層
23の厚さおよび処理温度によって制御可能である。上
述した具体的な数字はこの一例である。しかし、本発明
の原理はこの値の場合に限られるものではなく、それぞ
れの場合に実験により前辺って選択することが可能であ
る。
Incidentally, the spikes 26 penetrate through the amorphous layer 25 from the surface of the substrate 21 as shown in the figure, but the spikes 26 pass through the amorphous layer 25 from the surface of the substrate 21.
It is formed so that it does not pass through and reach the bulk of the substrate 21. The formation of such spikes can be controlled by the thickness of the pure aluminum layer 23 and the processing temperature. The specific numbers mentioned above are just one example. However, the principle of the invention is not limited to this value; it can be selected experimentally in each case.

なお拡散層の深さは上記例において3000人〜600
0人の深さに形成した。
Note that the depth of the diffusion layer is 3000 to 600 in the above example.
Formed to a depth of 0 people.

次にシリコンを1〜2%含有するアルミニウム層27を
1μmの厚さに付着して配線金属と拡散層とのコンタク
トを形成しく同図(b))、この後は通常の方法でPS
Gカバー膜、電極パンFなどを形成して半導体装置を完
成する。
Next, an aluminum layer 27 containing 1 to 2% silicon is deposited to a thickness of 1 μm to form a contact between the wiring metal and the diffusion layer (Figure (b)). After this, PS is applied in the usual manner.
G cover film, electrode pan F, etc. are formed to complete the semiconductor device.

(7)発明の効果 以上詳細に説明した如く、本発明の方法によれば、アモ
ルファス層と純粋アルミニウムとの反(6) 応によって形成されるスパイクが、金属配線と拡散層と
のコンタクトを良好にするため、従来問題とされたコン
タクト抵抗増大を防止することができ半導体装置の改善
に効果大である。
(7) Effects of the Invention As explained in detail above, according to the method of the present invention, the spikes formed by the reaction between the amorphous layer and pure aluminum (6) improve the contact between the metal wiring and the diffusion layer. Therefore, it is possible to prevent an increase in contact resistance, which has been a problem in the past, and is highly effective in improving semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の配線金属と拡散層とのコンタクト形成方
法を説明するための半導体装置要部の断面図、第2図は
本発明のコンタクト形成方法を実施する工程における半
導体装置要部の断面図である。 1.21−・・半導体基板、2.22−・PSG膜、3
.24−拡散層、4.2訃−アモルファス層、5.27
− シリコン含有アルミニウム配線層、26− スパイ
ク (7) 第1図 □ (b) □ □ (C) 第2図 □ −
FIG. 1 is a cross-sectional view of a main part of a semiconductor device for explaining a conventional method for forming a contact between a wiring metal and a diffusion layer, and FIG. It is a diagram. 1.21-・Semiconductor substrate, 2.22-・PSG film, 3
.. 24-Diffusion layer, 4.2-Amorphous layer, 5.27
- Silicon-containing aluminum wiring layer, 26- Spikes (7) Fig. 1 □ (b) □ □ (C) Fig. 2 □ -

Claims (1)

【特許請求の範囲】[Claims] 半導体装置における金属配線と拡散層との接触部形成方
法において、上記拡散層表面上の自然酸化膜を除去する
前処理工程を行なった後に純粋アルミニウムを配線領域
に付着する工程、次いでシリコン含有アルミニウムから
成る配線金属層を付着形成する工程を含むことを特徴と
する半導体装置の製造方法。
A method for forming a contact portion between a metal wiring and a diffusion layer in a semiconductor device includes a step of attaching pure aluminum to the wiring region after performing a pretreatment step of removing the natural oxide film on the surface of the diffusion layer, and then a step of attaching pure aluminum to the wiring region. 1. A method of manufacturing a semiconductor device, comprising the step of depositing and forming a wiring metal layer.
JP57113117A 1982-06-30 1982-06-30 Manufacture of semiconductor device Pending JPS594014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57113117A JPS594014A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57113117A JPS594014A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS594014A true JPS594014A (en) 1984-01-10

Family

ID=14603939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57113117A Pending JPS594014A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS594014A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187192A (en) * 2013-03-22 2014-10-02 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187192A (en) * 2013-03-22 2014-10-02 Toshiba Corp Semiconductor device

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