JPS5941765U - Performance board for IC tester - Google Patents

Performance board for IC tester

Info

Publication number
JPS5941765U
JPS5941765U JP13854882U JP13854882U JPS5941765U JP S5941765 U JPS5941765 U JP S5941765U JP 13854882 U JP13854882 U JP 13854882U JP 13854882 U JP13854882 U JP 13854882U JP S5941765 U JPS5941765 U JP S5941765U
Authority
JP
Japan
Prior art keywords
tester
wiring pattern
performance board
metal layer
selectively deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13854882U
Other languages
Japanese (ja)
Inventor
佐山　奉正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP13854882U priority Critical patent/JPS5941765U/en
Publication of JPS5941765U publication Critical patent/JPS5941765U/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＩＣテスタ用パーフオマンスボードの製
造方法を説明するための断面図、第２区はパーフオマン
スポード上に形成された接点部分と配線パタニンの一例
を示す平面図、第３図は第２図に示すＡ−Ａ線上の拡大
断面図、第４図はこの考案によるパーフオマンスポード
の製造工程中の一例を示す拡大断面図、第５図はこの考
案によるパーフオマンスポードの構造を示す拡大断面図
である。 １：絶縁基板、２：銅箔、４：メッキレジスト層、５：
貴金属層、６：接点部分、７：配線パターン、８：半田
層。FIG. 1 is a cross-sectional view for explaining a conventional method of manufacturing a perf-oman board for an IC tester, the second section is a plan view showing an example of the contact portion and wiring pattern formed on the perf-oman board, and the third The figure is an enlarged sectional view taken along the line A-A shown in Fig. 2, Fig. 4 is an enlarged sectional view showing an example of the manufacturing process of the perf-oman spode according to this invention, and Fig. 5 is the structure of the perf-oman spode according to this invention. FIG. 1: Insulating substrate, 2: Copper foil, 4: Plating resist layer, 5:
Noble metal layer, 6: Contact portion, 7: Wiring pattern, 8: Solder layer.

Claims (1)

【実用新案登録請求の範囲】 Ａ　接点部分に選択的に被着形成された貴金属層と、 Ｂ　配線パターン上に選択的に被着形成され上記配線パ
ターンを形成する場合のエツチングレジスト層として利
用され、エツチング後に加熱溶解されて周辺が上記配線
パターンのエツチング断面に溶着された状態にある半田
層と、を具備して成るＩＣテスタ用パーフオマンスボー
ド。[Scope of Claim for Utility Model Registration] A. A precious metal layer selectively deposited on the contact portion, and B. A noble metal layer selectively deposited on the wiring pattern and used as an etching resist layer when forming the wiring pattern. A performance board for an IC tester, comprising: a solder layer which is heated and melted after etching so that its periphery is welded to the etched cross section of the wiring pattern.
JP13854882U 1982-09-13 1982-09-13 Performance board for IC tester Pending JPS5941765U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13854882U JPS5941765U (en) 1982-09-13 1982-09-13 Performance board for IC tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13854882U JPS5941765U (en) 1982-09-13 1982-09-13 Performance board for IC tester

Publications (1)

Publication Number Publication Date
JPS5941765U true JPS5941765U (en) 1984-03-17

Family

ID=30310832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13854882U Pending JPS5941765U (en) 1982-09-13 1982-09-13 Performance board for IC tester

Country Status (1)

Country Link
JP (1) JPS5941765U (en)

Similar Documents

Publication Publication Date Title
JPS5815957B2 (en) Manufacturing method of printed wiring board with contacts
JPS6020163U (en) printed wiring board
JPS6141272Y2 (en)
JPS61264783A (en) Printed wiring board and manufacture thereof
JP2739123B2 (en) Manufacturing method of electronic component mounting board
JPS58213451A (en) Forming method for multilayer wiring
JPS583067U (en) printed wiring board
JPS6096868U (en) printed wiring board
JPS58173266U (en) multilayer printed wiring board
JPH0548257A (en) Printed circuit board manufacturing method
JPS6232684A (en) Manufacture of printed circuit board
JPS58147273U (en) Solder plated printed wiring board
JPS58191661U (en) printed board
JPS583066U (en) printed wiring board
JPS6088575U (en) Printed board
JPS6226074U (en)
JPS60103863U (en) printed board
JPS63187687A (en) Manufacture of printed wiring board
JPS6142879U (en) Printed board
JPS5952523U (en) Printed circuit board switch pattern
JPS6048271U (en) electrical circuit board
JPS6343480U (en)
JPS62211986A (en) Manufacture of printed wiring board
JPS5812966U (en) flexible printed wiring board
JPS61100168U (en)