JPS5942692A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To facilitate and stabilize the control, by providing a means which holds the drain potential of a transistor (TR), which receives an external main clock by the gate and has the source grounded and has the drain connected to the source of an output TR, in a low level during the self-refresh period in an artificial static RAM. CONSTITUTION:An internally generated self-refresh start clock ATRE and an external refresh control clock RFSH are inputted to a control circuit 10, and the output becomes high-level by receiving the first clock ATRF in the self-refresh mode, and the high level is held during the period of the self-refresh mode. A TR 11 which uses this output as the gate input is connected in parallel with a TR 6, and a node N5 is low-level independently of the level of a clock CE. Even if the level of the clock CE is varied to cut off TRs 4 and 6, the level of a node N6 is high, and the clock CE is reset. Since the level of the external refresh control clock is only held and the variance of the external main clock can be ignored, the control is facilitated and the operation is stabilized.

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

Random access memories (hereinafter referred to as RA, M) include static RAM, which does not require refreshing information stored in memory cells, and dynamic RAM (hereinafter referred to as DRAM), which requires periodic refreshing. DRAM
Refresh is generally done using the main clock externally.
This is done by adding an address input, but it has drawbacks such as the need to add a refresh control circuit to the memory system and the need to add inputs with strict timing such as the main clock and address. Pseudo static RAM (hereinafter referred to as P8AM) is a type of RAM that eliminates these drawbacks. PSRAM is a storage device that includes a refresh control circuit and a refresh address counter, and can be internally refreshed using only an external refresh control clock (hereinafter referred to as RFSH). When PSRAM is used, the memory system becomes simpler because the complicated refresh control circuit can be omitted.
There is an advantage that there is no need to update multiple clocks with strict timing for refreshing.

Since PSRAM is a semi-static RAM, the information in the memory cells must be maintained correctly even when it is not accessed for a long time, such as during battery backup, which is different from normal standby. For this purpose 1
'SRAM is set to 1 when the battery is up.
It has a function (self-refresh function) of refreshing itself at a constant cycle inside the device. The present invention relates to this self-refresh.

The internal IJ freshier is performed by activating itFSL (7L level in this case).When activating 1tFll, the level state of the main clock is always @HW as shown in Figure 1. There are two cases: the case where it has to be ``H'' or ``L'' as shown in Figure 2, and the case where it can be either ``H'' or ``L''. , the first-stage clock generation circuit (hereinafter referred to as CE generation circuit) of the main clock system is reset and precharged.

In the latter case, clocks for confirming the completion of read, write, and refresh operations are generated internally, and the CE
The generation circuit is reset and precharge is automatically performed regardless of the level of the main clock at that time. The latter is advantageous in terms of the degree of freedom of the main clock.

FIG. 3 shows a conventional CE generation circuit and its control circuit having an automatic precharge function using an N-channel MO8 transistor. CE is the main clock (hereinafter CE will be referred to as main clock), and CE is the main system first stage clock. RF11P 1.几1" ED is a system clock, and RP "1" is activated during the refresh operation and maintains the "it" level, P)?
, x are precharge clocks having a level opposite to that of F1.

I? , DED, WILED, It, and FED are operation completion confirmation clocks, which correspond to read, write, and refresh operations, respectively. The RFED also has the function of resetting the refresh system clock generation circuit. In this figure, 1 is a CE generation circuit, and 2 and 3 are its first control circuit and second control circuit.

FIG. 4 shows each input waveform and each node waveform when the operation shown in FIG. 1 is performed. As you can see from this diagram,
To reset the CE generation circuit 1 by changing the level of CE from IL' to W)l, the CE generation circuit 1
Furthermore, if the second control circuit 3 and transistor 4 are configured as shown in FIG. 3, automatic precharging immediately after the CE level change shown in FIG. 2 can be realized. . White in Figure 5! The winter input waveform and the waveforms of each node in the case of Rippurichi Y-ji are shown. In the figure, the active period of υCE is lengthened, and CE becomes 'L'.
Indicates that precharging is also performed on L/bevel. This automatic precharge circuit has already been proposed. (Patent application No. 56-142740). This circuit can handle self-refresh during battery backup.

Note that there are problems as described below.

When the self-refresh (RFS) 1 is kept activated for a certain period of time, the self-refresh activation clock A '1' RF is periodically generated by the built-in timer, and refresh is automatically performed each time. RFSH
As long as the activation continues, refresh and precharge are repeated.

FIG. 6 shows each input waveform and each node waveform at the time of self-refresh when the CE generating circuit 1 and the first control circuit 2 are configured in FIG. 3 as the first case without freezing. tωK
Refreshing is performed once when RF 8 H is activated. At this time, node N11j = I, the transistor 5 branch is cut off at I level. When the refresh is completed, the refresh clock generation circuit (not shown) is reset and the RF signal is generated.
I goes to 1L" level and PR,1 goes to 'H" level. Therefore, the % node N1 goes to the "H" level, and the transistor 5 becomes conductive. Since the transistors 5 and 6 (corresponding to the first transistor) reset the CE generation circuit 1, the VC to be reset CE must be at "H" level. R1・'S
If the activation of H is maintained, the timer starts t6.
1 self-refresh startup clock A 'J' 1L
Ii'' is generated, the refresh system clock generation circuit is activated, and RF 1 goes to H' level, )) I also changes to 1 and goes to the same level. Therefore, the node N1 becomes 11J level, and the transistor 5 becomes In the cut-off state, #) CE is generated and a refresh operation is performed. When the refresh operation is completed, the state returns to the reset state. According to the timer set during the refresh operation, AT RF is generated again at time t63.
The same thing is repeated. At time 162, when node N1 is at the "H" level and CE is in the reset state, a level change occurs in CB as shown at 61, and the level changes from lJI to IL.
1 and continues until time t64. CE at 162
The generating circuit 1 becomes set and generates CB. At this time, the refresh system clock generation circuit is in a reset state, so the read system or write system clock generation circuit is activated and the memory cell designated by the external address is accessed. When the external write control clock is activated, the contents of the memory cell may be rewritten.

Furthermore, if the activated state of CE continues until t64, the CE generation circuit 1 cannot be reset, and the refresh request at time tea is ignored until the CE is generated.

From the above, when using only the first control circuit 2, the level of CE at the time of self-refresh must be l111, and fluctuation is not allowed.

Next, as a second case, FIG. 7 shows each input waveform and each node waveform when the second control circuit 3 for the automatic precharge machine 41 is added. In this figure, CE is activated at t70 as shown in 71, and F'S) is activated at t71 while keeping it in the 'L level state.At this time, the interval between tyo and 171 is sufficient, and at t71 It is assumed that precharging is completed and refresh is started immediately by activation of FSH.When RF SH is activated at t7., the refresh system clock generation circuit is activated and refresh is performed, and R , FED, the refresh system clock generation circuit and CE generation circuit 1 are reset. In this reset state, CE is "H".
When CE is lJ, it is maintained through transistors 5 and 6 as in the first case, and when CE is I, it is maintained through transistors 4 and 5. ATR,I" is generated at t72, and self-refresh is performed. CE generation circuit 1 after refresh
The reset method is the same for different CE levels. C during the precharge period from t73 to t74
The variation of E is shown in 72 from "L" level to 1
■] Changes to the rubel are allowed. This is because the maintenance of the reset state of CB, which used to be performed through transistors 4 and 5, has been changed to only transistors 5 and 6, and the CE generation circuit IK has no effect. However, fluctuations from the 1H level to the ILI level beyond that indicated by 73 are not allowed.

When CE is at “H” level, the second control circuit 3 in Fig. 3
As shown at 74, the node N3 becomes an IL level and does not fulfill its function. CE reset is transistor 5
and transistor 6, which is the same as in the first case. CB Ka" From H'level'
When the level changes to "L", the transistor 6 is cut off and CE occurs, and the contents of the memory cell may be rewritten as in the first case.
Due to the change in E, the node N3 becomes 1L level as shown by 75, and the node N3 becomes -Kl'' level when the FED is generated in the state of CB5f'J,' level in the next refresh. Therefore, it is not allowed for CE to fluctuate to IL' level again until t74, as this will result in the occurrence of CE.In this way, even if CE fluctuations are conditionally allowed, battery backup It is inconceivable that the voltage should be varied while satisfying this condition over a long period of time such as the current level, and in the end it must be fixed at the level of either °)i'' or IL'.

As mentioned above, in self-refresh during battery backup, when using the first control circuit 2 shown in FIG. When using the circuit 2 and the second control circuit 3, the level of CB must be maintained at either "H" or "L". In either case, over a long period of time, Rli"SH and CB There is a problem in that the levels of the two clocks must be maintained strictly.

An object of the present invention is to provide means for maintaining the drain potential of the transistor 6 (corresponding to the first transistor) at a low level during the self-refresh period, thereby solving the aforementioned problems and facilitating control. The object of the present invention is to provide a PSRAM that operates stably.

The device of the present invention has an external main clock and an external refresh control clock as inputs, and performs internal refresh by activating the external refresh control clock.
and a self-refresh mode in which a self-refresh activation clock is generated by a built-in timer and internal refresh is automatically repeated as long as the external control clock is kept active;
A semiconductor memory including a main clock system first-stage clock generation circuit including a first transistor whose gate receives the external main clock, whose source is grounded and whose drain is an output, and a control circuit that controls the main clock system first-stage clock generation circuit. The device comprises control means for maintaining the drain/potential of the first transistor at a low level during the self-mode refresh period.

Further, in the device of the present invention, the control means may include the external fJ refresh control clock and the self-refresh first one.
・The output of the auxiliary control circuit goes to a high level in response to the cell 7 refresh activation clock generated in the cell 7 refresh mode. Therefore, when the external refresh control clock is deactivated, it becomes a low level.

The present invention will be explained in detail below with reference to the drawings.

FIG. 8 shows a circuit diagram of an embodiment of the present invention. These 19 cells 2 and 3 have the same contents as the first and second control circuits 2 and 3 in FIG. 3, respectively, and the transistor numbers and node numbers also match those in FIG. 3. An auxiliary control circuit 10 and a transistor 11 (corresponding to a second transistor) are added according to the present invention.

FIG. 9 shows each input waveform and each node waveform in FIG. 8. Next, the operation of this embodiment will be explained using FIGS. 8 and 9.

Refreshing is performed when 1'LFSH is activated at time 190. This refresh is It Ii”
The activation of SR is a refresh (pulse refresh) that is not caused by ATR and F. When , the level of the main clock CE may be either 1H''I] or I, and after the time t91 when refresh is completed''
If it is 11", the transistor 5 and transistor 6 are all passed through, and if it is 'L1, the CE is reset through the transistor 4 and transistor 5. If CE is 1 like 92,
When the voltage changes from "L" to 11I"K, a reset occurs through transistors 4 and 5.

It changes into a set through transistor 5 and transistor 6. A timer is set during refresh operation,
The timing operation is performed while RF8H is in the active state.

The self-refresh mode is activated when 1(,B''8H) remains activated until after time t93 when ATRF is internally generated, and before that, RF8
When H is deactivated as in 93, it is in pulse refresh mode, the cycle ends, and the standby state is set for the next access or pulse refresh. R1! ' When entering the self-refresh mode while maintaining the activated state of S H, the pulse refresh cycle is maintained until Ai'l(,li'' is generated at time tc+a, and therefore the level of CE remains unchanged until t93. 1111 or 1L1, or a change from IHI to w 1. is only allowed from 'L' to IH'.
Changes to w are not allowed.

A 'II'RF' is internally generated at P1 time t93,
Like self-refreshment 12. As shown in FIG. 8, when the transistor 1 whose gate input is the output of the auxiliary control circuit 10 is placed in a string with the transistor 6 whose gate input is CE, the node N5. is not related to the level of CE (I L = level. CE is set/reset as follows. ATR・F is generated and the refresh system clock generation circuit is activated.
RF 1 Ka'H' Ni, P It 175f'
When it becomes L', the node N1 becomes lJ, level, so the transistor 5 is cut off, CE becomes IHI level, and refreshing is performed. Refreshing has finished and it is time t94! ? , FED is generated, the refresh system clock generation circuit is reset, and
'1 is at the 1L'' level, P 1 is at the wH level, and the node N
Transistor 5 becomes conductive at 11 level. At this time, if CE is 1, H, then CB becomes conductive through transistors 5, 6, and 11, so transistors 5 and 4, CF is reset.C
Time t95 when B is reset and in a precharge state and time tt16 when the next A'l'R and F are generated.
CB fluctuates from the IL'' level to 1 level as shown in 94, and the node N3 changes to K''l,'' as shown in 95. After the transistor 4 becomes in the cut-off state, the IL level changes again. Since the transistor 11 continues to be conductive, CB is still at AT.
As long as RF is generated, the 114 level is maintained.
Due to the inactivation ratio of S
It does not affect the operation of the 10 modes.

As explained above, the conventional CE generating circuit 1 which is connected at point 12 in FIG. 8 and its f:A 1. Second control circuit 2
, 3, Confessions of the present invention 3 The self-refresh start clock ATRF and the external refresh control 10 clocks
p s il is taken as an input, and its output becomes the "1]" level upon the occurrence of the first A T It J = " in the self-refresh mode, and maintains the 1110 level during the self-refresh mode. 'S
By adding an auxiliary control circuit 1o which becomes "L level" by deactivating H, and a transistor 11 connected in parallel with the transistor 6 whose gate input is the output of the auxiliary control circuit 1o and whose gate input is Cp, the self-refresh mode can be activated. The number of external clocks that are required to maintain their level during the period is conventional 1 (, FSI (and CE), SFC, and (D
The effect is that only one RF8N is required.

Fig. 10 shows the Ai'F and I (1O8) of the present invention from the auxiliary control circuit 10 that inputs I''SH to the N channel.
(An example is shown in which transistors are formed.Transistor 1
It consists of three sets of inverter circuits composed of inverter circuits 3 to 18 and a transistor 19. Next, the H.71 operation of this circuit will be explained using the input waveform and each node waveform diagram shown in FIG.

In Fig. 11, from time t1]0 to time t111 is RF.
This is a pulse refresh mode period in which refresh is performed by activation of SH. During this period, ATR
F is not generated and the I-1' level of It F S H is pulsed to the gate of transistor 18, so that node N6. N7 is at the IL" level and the node N8 is
Maintained at Hl level. It at time t111
I'' S H is activated and pulse refresh is performed, and even after completion of the pulse refresh, the active state of RF S H is maintained in order to enter the self-refresh mode, but the pulse refresh mode is still active and the node N6. N7
is l L l level, node N8 is 11 (Level).

At time t112, ATILF 110 is generated and the self-refresh mode is entered. If the dimension of transistor 15 is made larger than that of transistor 16, node N8 becomes 'H' before time t112.
Even if the transistor 16 is in a conductive state, the transistor 15 which receives the first generated ATILF 110 at its gate brings the node N7 to the IH" level, and the transistor 17 whose gate input is the node N7 The node N6 also goes to the lH'' level, so the transistor 14 becomes conductive, and the node N8 goes to the lLl level.
By maintaining the "Sll level at 1L" and periodically applying ATRF to the gate of the transistor 15,
11 of nodes N 7 and UN 6 (the level has been refreshed, and the output level of the auxiliary control first circuit 10 does not decrease. At time tl13, the deactivation of It F S 11 indicates the end of the refresh mode. , the transistor 18 becomes conductive, the node N6 reaches the sl,w level, and the node N8 reaches the ')Jl level.

As explained above, A1゛几F of the present invention shown in FIG.
Simple auxiliary control circuit 10 with inputs H and FSII
and a transistor 11 whose gate input is the output of this circuit.
When applied to the CE generation circuit 1, the level fluctuation of the external main clock during the reself-refresh mode can be ignored.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this embodiment, and the point is that the drain potential of the first transistor of the CB generation circuit is set to a low level in the self-refresh mode. Needless to say, it is sufficient to maintain the value at 1000, and this can also be achieved by using other suitable circuits.

The device of the present invention described in detail below is equipped with means for maintaining the drain potential of the first transistor of the CE generation circuit at a low level during the self-refresh period, so that it is not necessary to use an external There is no need to strictly maintain the levels of the two control clocks, the main clock and the external refresh control clock, and fluctuations in the external main clock can be ignored by simply maintaining the level of the external refresh control clock, making control easy. It is possible to provide a semiconductor memory device having a pseudo-static RAM function that operates stably, and its effects are significant.

[Brief explanation of drawings]

Figures 1 and 2 are time charts showing the relationship between the main clock CE and the external refresh clock ItI'SH, and Figure 3 shows a conventional CE generation circuit with an automatic precharge function and its control circuit. Circuit diagram shown, 4th
7 to 7 are waveform diagrams of each input and each node showing the operation of the circuit shown in FIG. 3, FIG. 8 is a circuit diagram of an embodiment of the present invention, and FIG. 9 is a circuit diagram of the circuit shown in FIG. FIG. 10 is a waveform diagram of each input and each node showing the operation, and FIG.
FIG. 11 is a circuit diagram showing one embodiment of the control circuit, and is a waveform diagram of each input and each node showing the operation of the circuit of FIG. 10. 1... Main system first stage clock generation circuit (CI'
, generation circuit), 2...first control circuit, 3...
...Second control circuit, 4...Transistor included in the second control circuit, 12...Conventional CE generation circuit and its peripheral control circuits, 13-18...
...transistor included in the third control circuit, 61.7
0 to 75, 91 to 95... Change in waveform or level, Nl to N8... Node. 7'i't Su 7'/ 4-f-Shi"nofu Lyzu"fi 7'! ＃r-Figure 1)'h-Jifu is doing hair-
Ji8ZZuyu'3 Ward T N2. N3 5th picture 6 Figure-552-

Claims (2)

[Claims] (1) A pulse refresh mode that has an external main clock and an external refresh control clock as inputs and performs internal refresh by activating the external refresh control clock, and a pulse refresh mode that uses a built-in timer as long as the external control clock is activated. The self-refresh mode has a self-refresh mode in which a self-refresh startup clock is generated and internal refresh is automatically repeated. In a semiconductor memory device including a main clock system first-stage clock generation circuit including one transistor and a control circuit for controlling the main clock system first-stage clock generation circuit, the drain potential of the first transistor is kept low during the self-refresh mode period. Be equipped with control means to keep it at level! Semiconductor storage device with characteristics (2) The control means comprises an M2 transistor whose gate is connected to the output of the external refresh control, whose drain is connected to the drain of the first transistor, and whose source is grounded, and the output of the auxiliary control circuit. Claim (1), characterized in that: becomes high level in response to the self-refresh activation clock generated in the self-refresh mode, and becomes low level when the external refresh control clock is deactivated. The semiconductor storage device described in 1.