JPS594591U - display device - Google Patents

display device

Info

Publication number
JPS594591U
JPS594591U JP9938182U JP9938182U JPS594591U JP S594591 U JPS594591 U JP S594591U JP 9938182 U JP9938182 U JP 9938182U JP 9938182 U JP9938182 U JP 9938182U JP S594591 U JPS594591 U JP S594591U
Authority
JP
Japan
Prior art keywords
display
screen
display device
range
suppression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9938182U
Other languages
Japanese (ja)
Inventor
坂本 嗣男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9938182U priority Critical patent/JPS594591U/en
Publication of JPS594591U publication Critical patent/JPS594591U/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、−従来の表示装置のブロック図、第2図は、
従来の画面重ね合せ表示の原理図、第3図は、本考案の
表示原理図、第4図は本考案の一実施例の表示装置のブ
ロック図、第5図C$本考案の一実施例の表示抑止回路
のブロック図である。 600・・・表示抑止回路、610,620・・・レジ
スタ、630・・・比較回路、640,650・・・A
NDゲート。
FIG. 1 is a block diagram of a conventional display device; FIG. 2 is a block diagram of a conventional display device;
Figure 3 is a diagram of the principle of a conventional screen overlapping display; Figure 3 is a diagram of the display principle of the present invention; Figure 4 is a block diagram of a display device according to an embodiment of the invention; Figure 5 is an embodiment of the invention. FIG. 2 is a block diagram of a display suppression circuit of FIG. 600...Display suppression circuit, 610,620...Register, 630...Comparison circuit, 640,650...A
ND gate.

Claims (1)

【実用新案登録請求の範囲】 1 文字、図形等から構成される画面を表示する装置に
おいて、表示画面の1部を他のもう一方の画面に重ね合
せたり、重ね合せなかったりの。 指示をする表示抑止コードと、その範囲を記憶する表示
抑止範囲レジスターを設け、前記表示抑止コードの内容
に従って前記表示画面を処理して表示することを特徴と
する表示装置。 2 前記表示抑止コードの内容に従い、前記表示画面の
ビデオ信号出力範囲を制御することを特徴とする実用新
案登録請求の範囲第1項記載の表示装置。
[Claims for Utility Model Registration] 1. In a device that displays a screen consisting of characters, figures, etc., one part of the display screen may or may not be superimposed on another screen. A display device comprising a display suppression code for instructing and a display suppression range register for storing the range thereof, and processing and displaying the display screen according to the contents of the display suppression code. 2. The display device according to claim 1, wherein a video signal output range of the display screen is controlled according to the content of the display suppression code.
JP9938182U 1982-07-02 1982-07-02 display device Pending JPS594591U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9938182U JPS594591U (en) 1982-07-02 1982-07-02 display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9938182U JPS594591U (en) 1982-07-02 1982-07-02 display device

Publications (1)

Publication Number Publication Date
JPS594591U true JPS594591U (en) 1984-01-12

Family

ID=30235539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9938182U Pending JPS594591U (en) 1982-07-02 1982-07-02 display device

Country Status (1)

Country Link
JP (1) JPS594591U (en)

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