JPS5950090B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5950090B2 JPS5950090B2 JP8163777A JP8163777A JPS5950090B2 JP S5950090 B2 JPS5950090 B2 JP S5950090B2 JP 8163777 A JP8163777 A JP 8163777A JP 8163777 A JP8163777 A JP 8163777A JP S5950090 B2 JPS5950090 B2 JP S5950090B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor element
- film layer
- semiconductor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 本発明は、半導体ウェハと電極支持板を接合す。[Detailed description of the invention] The present invention joins a semiconductor wafer and an electrode support plate.
る構造の半導体装置の製造方法に関するものである。従
来の半導体装置は、Si等の半導体ウェハからなる半導
体エレメントをセラミック等の気密パッケージ内に収納
し、半導体エレメントの雰囲気の安定化を図ることによ
つて信頼性を上げているが、最近ではコストダウンの為
、高価な気密パッケージを廃し、ゴムリング等による簡
易パッケージの使用、さらには半導体エレメントそのも
のをフロン等の化学冷媒に直接浸漬して冷却する沸騰冷
却方式の適用も考えられるに至つている。The present invention relates to a method for manufacturing a semiconductor device having a structure. Conventional semiconductor devices improve reliability by housing a semiconductor element made of a semiconductor wafer such as Si in an airtight package made of ceramic or the like to stabilize the atmosphere of the semiconductor element, but recently the cost has increased. In order to reduce downtime, it is now possible to eliminate expensive airtight packages and use simple packages such as rubber rings, and even to apply boiling cooling methods in which semiconductor elements themselves are directly immersed in chemical refrigerants such as fluorocarbons. .
ところがこのような簡易パッケージ、沸騰冷却方式等を
適用する場合には、使用する雰囲気に耐えるように半導
体エレメントの電極を構成する必要が生じる。これを図
面について説明すると、第1図は従来の半導体エレメン
トの一例を示すもので、1はPN接合を有するSi基板
、2はSi基板1にAlろう材Sによりろう接された電
極支持板としてのMo板、4はオーミック接触を得るた
めにSi基板1に蒸着されたAl電極、5はSi基板1
のPN接合面の安定化を図る表面処理材料である。However, when such a simple package, boiling cooling method, etc. are applied, it is necessary to configure the electrodes of the semiconductor element to withstand the atmosphere in which it is used. To explain this with reference to the drawings, Fig. 1 shows an example of a conventional semiconductor element, in which 1 is a Si substrate having a PN junction, and 2 is an electrode support plate soldered to the Si substrate 1 with an Al brazing material S. 4 is an Al electrode deposited on the Si substrate 1 to obtain ohmic contact, 5 is the Si substrate 1
This is a surface treatment material that aims to stabilize the PN junction surface.
このような構造の半導体エレメントをそのまま気中で使
用する場合にはAl電極4およびMo板2の表面が酸化
してこの面に圧接される外部導体との接触抵抗が増大す
るおそれがあり、またこの半導体エレメントを前記のよ
うにフロン冷媒中で使用する場合には、フロンの熱分解
により生ずる酸によつてAl電極4が腐食される等の問
題が生じる。If a semiconductor element having such a structure is used as it is in the air, the surfaces of the Al electrode 4 and Mo plate 2 may be oxidized and the contact resistance with the external conductor pressed against these surfaces may increase. When this semiconductor element is used in a fluorocarbon refrigerant as described above, problems arise such as the Al electrode 4 being corroded by the acid produced by thermal decomposition of the fluorocarbon.
これらの欠点を解決するために酸化及び腐食に対し優れ
た特性を有する半導体エレメントを得るとともに、導電
性の良い電極を得る方法としてAu膜層を用いることが
考えられる。In order to solve these drawbacks, it is conceivable to use an Au film layer as a method to obtain a semiconductor element having excellent properties against oxidation and corrosion and to obtain an electrode with good conductivity.
ところが公知のようにSi基板1に直接Auでオーミッ
ク接触をとると、Auが徐々にSi基板1内に拡散し、
半導体エレメントの電気的特性に悪影響を与える。また
第1図に示すような半導体エレメントにおいてAl電極
4および電極支持板としてのMo板2上にさらにAu電
極およびAu保護膜をメツキで構成することも考えられ
るが、この場合には表面処理材料5がメツキ液に侵され
る結果特性不良をきたして歩留りが悪くなり、またMO
板2側にメツキされたAuは、A1ろう材3の融点で制
限される温度以上にジッタ(メツキまたは蒸着の後、こ
れを高温雰囲気中におき、メツキ蒸着金属の接合強度を
高める処理)できないことから、十分な付着強度が得ら
れず、Auメツキ効果が得られない。さらにAl電極4
上にメツキされたAuは、半導体エレメント使用時の発
熱温度で徐々にAl電極4と高抵抗の合金層を作り、電
気抵抗の増大をきたす等種々の問題が生じる。本発明は
、上記従来の半導体エレメンヒおよびその製造方法のも
つ欠点を除去するためになされたもので、上記不都合を
生じることなく、半導体エレメントの最外殼電極を酸化
及び腐食に対し非常に優れた性質を有するAu電極にす
るとともに、Au保護膜の形成された電極支持板にする
ことができる半導体装置の製造方法を提供することを目
白勺とする。However, as is known in the art, when direct ohmic contact is made with Au to the Si substrate 1, Au gradually diffuses into the Si substrate 1.
Adversely affects the electrical properties of semiconductor elements. It is also conceivable to further construct an Au electrode and an Au protective film by plating on the Al electrode 4 and the Mo plate 2 as an electrode support plate in a semiconductor element as shown in FIG. 5 is attacked by the plating solution, resulting in poor characteristics and poor yield.
The Au plated on the side of the plate 2 cannot jitter above the temperature limited by the melting point of the A1 brazing material 3 (a process in which after plating or vapor deposition, it is placed in a high-temperature atmosphere to increase the bonding strength of the plated vapor-deposited metal). Therefore, sufficient adhesion strength cannot be obtained and the Au plating effect cannot be obtained. Furthermore, Al electrode 4
The Au plated on top gradually forms a high-resistance alloy layer with the Al electrode 4 at the heat generation temperature when the semiconductor element is used, causing various problems such as an increase in electrical resistance. The present invention was made in order to eliminate the drawbacks of the conventional semiconductor element and its manufacturing method, and it provides the outermost electrode of the semiconductor element with extremely excellent properties against oxidation and corrosion without causing the above-mentioned disadvantages. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can produce an Au electrode having an Au electrode and an electrode support plate on which an Au protective film is formed.
本発明に係る半導体装置の製造方法は、半導体ウエハの
電極面および電極支持板下面に順次Al膜層、Ni膜層
、Au膜層を形成してこれら三層で電極を構成すること
により、半導体特性に優れ、かつ耐酸化性および耐腐食
性に優れた半導体装置を得るようにしたことに特徴を有
するものである。The method for manufacturing a semiconductor device according to the present invention includes sequentially forming an Al film layer, a Ni film layer, and an Au film layer on the electrode surface of a semiconductor wafer and the lower surface of an electrode support plate, and forming an electrode with these three layers. The present invention is characterized in that a semiconductor device with excellent characteristics, oxidation resistance, and corrosion resistance is obtained.
以下本発明の一実施例を図について説明すると、第2図
は本発明による半導体装置製造方法の一実施例を示すフ
ローチヤート、第3図はこのフローチヤートに則り、半
導体装置の一例としてのサイリスタを製造した場合の構
造を示している。An embodiment of the present invention will be explained below with reference to the drawings. FIG. 2 is a flowchart showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. This shows the structure when manufactured.
この両図に基き本発明の製造工程を順に説明する。(a
)合金完了エレメント
所定のPN接合を有するSi等の半導体ウエハと、これ
を支持するMO板等の電極支持板をA1ろう材等を介し
て周知の方法で接合し、半導体エレメントを構成した状
態である。The manufacturing process of the present invention will be explained in order based on these two figures. (a
) Alloy completed element A semiconductor wafer made of Si or the like having a predetermined PN junction and an electrode support plate such as an MO plate that supports it are joined by a well-known method via an A1 brazing material etc. to form a semiconductor element. be.
第3図ではSiウエハ1とMO板2をAlろう材3でろ
う接している。(b)Al蒸着上記(a)の半導体エレ
メントの両表面、すなわち半導体ウエハ電極面と電極支
持板表面にA1膜層を例えば10μ厚に真空蒸着して形
成する。In FIG. 3, a Si wafer 1 and an MO plate 2 are soldered together using an Al brazing material 3. (b) Al Vapor Deposition: On both surfaces of the semiconductor element in (a) above, that is, on the semiconductor wafer electrode surface and the electrode support plate surface, an Al film layer is vacuum-deposited to a thickness of, for example, 10 μm.
この場合の真空度は例えば10−3T0rrである。第
3図では符号4がこのAl膜層を示している。(c)ジ
ッタ
上記(b)のAl蒸着半導体エレメントを、例えば、N
2ガス中、560℃30分間の条件でジッタし、半導体
ウエハとのオーミツク接触を形成すると共に半導体エレ
メント両表面上のA1蒸着層の付着強度を高める。The degree of vacuum in this case is, for example, 10-3T0rr. In FIG. 3, reference numeral 4 indicates this Al film layer. (c) Jitter The Al-deposited semiconductor element of (b) above is replaced with, for example, N
Jittering is performed for 30 minutes at 560° C. in two gases to form ohmic contact with the semiconductor wafer and increase the adhesion strength of the A1 vapor deposited layer on both surfaces of the semiconductor element.
(d)Niメツキ
上記(c)の工程で半導体エレメントに強固に付着され
たAl膜層上に、Niを例えば1μ厚にメツキし、Ni
膜層を形成する。(d) Ni plating On the Al film layer firmly attached to the semiconductor element in the step (c) above, Ni is plated to a thickness of, for example, 1μ.
Form a membrane layer.
このNiメツキ層は下地のAl膜層とのこの後にメツキ
するAuとの間で高抵抗のAl−Au合金層が形成され
るのを防ぐバリヤとしての効果を得るものである。した
がつて厚みは最少限必要なだけで浪く、また緻密度の上
からも無電解メツキによつて形成することが望ましい。
第3図では6がこのNi膜層を示す。(e) Auメツ
キ
上記(d)工程においてNiメツキを施した半導体エレ
メント上に、Auを電解メツキで例えば2μ厚にメツキ
する。This Ni plating layer functions as a barrier to prevent the formation of a high-resistance Al--Au alloy layer between the underlying Al film layer and the subsequently plated Au layer. Therefore, it is desirable that the thickness be kept at the minimum required level, and that it be formed by electroless plating from the viewpoint of density.
In FIG. 3, 6 indicates this Ni film layer. (e) Au plating On the semiconductor element plated with Ni in the above step (d), Au is plated to a thickness of, for example, 2 μm by electrolytic plating.
このAuメツキ層は、電極の酸化および腐食を防ぐ保護
膜としての効果を得る為、比較的厚い方が望ましく、こ
の点で無電解メツキより電解メツキを用いる方が容易で
ある。第3図で゛は7がこのAu膜層を示す。(f)パ
ターンエツチング
以上の電極形成が終了した半導体エレメントに対し、半
導体ウエハの電極面において島状に独立した電極が必要
な場合には、A1−Ni−Au−三層構造の電極をそれ
ぞれに応じた薬品でパターンエツチングする。This Au plating layer is preferably relatively thick in order to obtain the effect of a protective film that prevents oxidation and corrosion of the electrode, and in this respect, it is easier to use electrolytic plating than electroless plating. In FIG. 3, 7 indicates this Au film layer. (f) For a semiconductor element for which electrode formation beyond pattern etching has been completed, if independent island-like electrodes are required on the electrode surface of the semiconductor wafer, separate electrodes with a three-layer structure of A1-Ni-Au- Pattern etching with appropriate chemicals.
例えば該半導体エレメントがサイリスタである場合には
Siウエハ側電極をゲート電極とカソード電極に分解す
る。第3図はこの電極の分離が行なわれた状態を示して
いる。またダイオードの場合にはこの工程(f)が必要
でないことはいうまでもない。(g)ベベル加工
上記(f)まででA1−Ni−Au三層構造の電極が完
成した半導体エレメントの半導体ウエハ周辺部において
、PN接合露出面を傾斜をつけ加工することにより表面
電界を低減する。For example, if the semiconductor element is a thyristor, the Si wafer side electrode is separated into a gate electrode and a cathode electrode. FIG. 3 shows the state in which this separation of the electrodes has taken place. It goes without saying that this step (f) is not necessary in the case of a diode. (g) Bevel processing In the semiconductor wafer periphery of the semiconductor element in which the A1-Ni-Au three-layer structure electrode has been completed in the above (f), the exposed surface of the PN junction is beveled and processed to reduce the surface electric field. .
ベベル加工方法は、例えばサンドブラスト、機械的研摩
等で行なう。第3図におけるSiウエハ1周縁の斜面8
はこのベベル加工によつて形成したものである。卸 表
面処理最後に上記1g)でベベル加工を施した半導体エ
レメントのベベル面に対し薬品エツチングを施した後、
例えばワニス等の表面処理材料を塗布してPN接合露出
面の表面安定化を図る。The bevel processing method is performed by, for example, sandblasting, mechanical polishing, or the like. Slope 8 at the periphery of the Si wafer 1 in Fig. 3
is formed by this bevel processing. Wholesale Surface treatment Finally, after applying chemical etching to the beveled surface of the semiconductor element that has been beveled in step 1g) above,
For example, a surface treatment material such as varnish is applied to stabilize the exposed surface of the PN junction.
第3図の5はこの表面処理材料を示している。以上のよ
うに形成した半導体装置は、第3図のように、Siウエ
ハ1の電極がAl−Ni−Au三層構造からなり、その
最外殻電極がAu電極7であることから、酸化および腐
食に強く、適当な表面処理材料5を選べば、このままの
状態で気中、あるいはフロン中等各種雰囲気中で使用で
きる。5 in FIG. 3 indicates this surface treated material. As shown in FIG. 3, the semiconductor device formed in the above manner is free from oxidation and If a suitable surface treatment material 5 that is resistant to corrosion is selected, it can be used as is in various atmospheres such as air or fluorocarbon.
またNi膜層6はAu膜層7とAl膜層4とのバリヤと
して働き、両金属による高抵抗のAl−Au合金の形成
を妨げるので長期に渡る信頼性が得られる。さらにMO
板2側のAl−Ni−Au電極はAl電極4がすでにジ
ッタされているので圧接構造で用いる装置として十分な
付着強度が得られている。なお上記の実施例では、半導
体エレメントの半導体ウエハ側の電極面のみならず、電
極支持板(MO板)表面にもAl−Ni−Au三層構造
の電極を形成したが、場合によつては、このMO板側、
すなわち電極支持板側表面には上記三層構造の電極を形
成せず、半導体ウエハの電極面のみにA1−Ni−Au
三層構造を形成するようにしてもよいことは言うまでも
ない。Further, the Ni film layer 6 acts as a barrier between the Au film layer 7 and the Al film layer 4, and prevents the formation of a high resistance Al--Au alloy by both metals, thereby providing long-term reliability. Furthermore, M.O.
Since the Al electrode 4 has already been jittered, the Al--Ni--Au electrode on the plate 2 side has sufficient adhesion strength as a device used in a press-contact structure. In the above embodiment, an Al-Ni-Au three-layer structure electrode was formed not only on the electrode surface of the semiconductor element on the semiconductor wafer side but also on the surface of the electrode support plate (MO plate). , this MO board side,
In other words, the three-layer structure electrode is not formed on the surface of the electrode support plate, and A1-Ni-Au is formed only on the electrode surface of the semiconductor wafer.
It goes without saying that a three-layer structure may be formed.
以上のように本発明によれば、半導体エレメントの半導
体ウエハの電極面および電極支持板表面にAl−Ni−
Auの三層構造の電極を形成することによつて、酸化お
よび腐食に対し非常に優れた半導体装置が得られ、した
がつて、簡易パツケージ、沸騰冷却方式等の条件下で使
用する半導体装置の製造に利用して特に好適である。As described above, according to the present invention, Al-Ni-
By forming an electrode with a three-layer structure of Au, a semiconductor device that is extremely resistant to oxidation and corrosion can be obtained. It is particularly suitable for use in manufacturing.
第1図は、従来の半導体エレメントを示す断面図、第2
図は、本発明に係る半導体装置の製造方法の実施例を示
すフロチヤート、第3図は、本発明による半導体装置の
製造方法によつて得られた半導体装置の一例を示す断面
図である。
1 ・・・・・・半導体ウエハ、2 ・・・・・・電極
支持板、3 ・・・・・・Alろう材、4・・・・・・
All膜層、6・・・・・・Ni膜層、7 ・・・・・
・Au膜層、なお図中、同一符号は同一または相当部分
を示す。Figure 1 is a sectional view showing a conventional semiconductor element, Figure 2 is a sectional view showing a conventional semiconductor element;
The figure is a flowchart showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 3 is a sectional view showing an example of a semiconductor device obtained by the method for manufacturing a semiconductor device according to the present invention. 1... Semiconductor wafer, 2... Electrode support plate, 3... Al brazing material, 4...
All film layer, 6... Ni film layer, 7...
・Au film layer: In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
して半導体エレメントを形成し、この半導体エレメント
の上記半導体ウェハ電極面に、順次Al膜層、Ni膜層
、Au膜層を積層して三層構造の電極を形成するととも
に、上記電極支持板表面に上記三層構造の保護膜を形成
することを特徴とする半導体装置の製造方法。1. A semiconductor element is formed by bonding an electrode supporting plate to a semiconductor wafer having a PN junction, and an Al film layer, a Ni film layer, and an Au film layer are sequentially laminated on the semiconductor wafer electrode surface of this semiconductor element to form a three-layer structure. A method for manufacturing a semiconductor device, comprising forming an electrode having a three-layer structure, and also forming a protective film having a three-layer structure on a surface of the electrode support plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8163777A JPS5950090B2 (en) | 1977-07-07 | 1977-07-07 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8163777A JPS5950090B2 (en) | 1977-07-07 | 1977-07-07 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5416979A JPS5416979A (en) | 1979-02-07 |
| JPS5950090B2 true JPS5950090B2 (en) | 1984-12-06 |
Family
ID=13751840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8163777A Expired JPS5950090B2 (en) | 1977-07-07 | 1977-07-07 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950090B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6089418A (en) * | 1983-10-20 | 1985-05-20 | Sumitomo Chem Co Ltd | Sustained release carcinostatic agent |
| JP2007194514A (en) | 2006-01-23 | 2007-08-02 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
| JP2010021171A (en) * | 2008-07-08 | 2010-01-28 | Renesas Technology Corp | Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used for the same |
-
1977
- 1977-07-07 JP JP8163777A patent/JPS5950090B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5416979A (en) | 1979-02-07 |
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