JPS5950558A - Static type memory device - Google Patents

Abstract

PURPOSE:To reduce wiring resistance by a method wherein a power source line and a load resistor are arranged in an array of memory cells, and then the maximum value of the length of a data line from a point of the connection of the load resistor to a point of the connection of the memory cell is reduced. CONSTITUTION:Each of load resistors R11, R12-Rm1, Rm2 is connected to each of the data lines di at the center of the memory cell array CA, i.e., the position for nearly equally dividing n-pieces of memory cells Mi,k connected in common to each of the data lines di into subgroup (the medium point of the data lines di). The power source line VDD is also arranged in the direction rectangular to the data lines di at the center of the memory cell array CA and then connected in common to the load resistors R11, R12-Rm1, Rm2. As the result, the influence by the resistance of the data lines di is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and particularly to a semiconductor static type memory device that is excellent in speeding up and stabilizing operation.

[Prior art]

FIG. 1 shows a portion of a cell array and its peripheral portion of a conventional semiconductor static memory device. That is, in the figure, %Mx, t=Mrn, n is mxn memory cells, and by arranging them regularly in a matrix, a cell array CA consisting of n rows and m columns is created.
is configured. (Memory cell M, A is the
Corresponds to the row memory cells. )'i Also, in the figure,
W1 to Wn are word lines commonly connected to the memory cells in the first to nth rows, respectively;
n are word drivers, dl, driving word lines W+"Wn, respectively;

d1 to dm, (Im is the data line % commonly connected to each memory cell in the column corresponding to the subscript. R111°R1
2~TIt, Rr++4 is the load resistance of the data line arranged outside the cell array and connected to each of the data lines d1 + d1~dm, dm, and VDD is the load resistance of the above 2m load resistances Rx2~Rmx * Rmz The power supply lines SA1 to SAm commonly connected to the sense amplifiers, CD, and SAm connected to the data line pairs corresponding to the respective subscripts
CD is a common data line connected to sense amplifiers SAI to S A m, and OB is a common data line connected to sense amplifiers SAI to S A m.
The output buffers D and CD are connected, and DO is an output terminal connected to the output buffer OB.

Next, a read operation of this memory device will be briefly explained. By a signal applied to an address input terminal (not shown) of the memory device, one of the word lines W1 to Wn is set to a potential that makes the memory cell selected, and the other word lines are set to a potential that makes the memory cell non-selected. The potential is set to the state. As a result, a signal appears on each pair of data lines corresponding to the information held in each of the memory cells connected to the selected word line. Further, one of the sense amplifiers 8At to SAm is selected by a signal applied to the address input terminal of the memory device,
The signal appearing on the pair of data lines connected to the sense amplifier is amplified by the selected sense amplifier and transmitted to the common data IcD, CD. Finally, the common data gcD and CD signals are amplified and waveform-shaped by the output sofa OB and output to the output terminal. A signal appears and reading is completed.

Next, the mechanism by which a signal is generated on the data line during reading will be briefly described. The second section 1 shows one specific example of a memory cell in a part of FIG. 1. In the figure, the area surrounded by dotted lines is the memory cell.
This is Ml in Figure 1.

~M m , corresponds to one of n. In Figure 2,
W is one of Wl, -Wn in Figure 1, d is dl in Figure 1
-dm, d in Figure 1, -dm, P
, I correspond to one of the boxes 11 to ml in FIG. 1, and the box 2 corresponds to one of R1□ to Rm2 in FIG. 1, respectively. In addition, in FIG. 2, the memory cell is composed of six field effect transistors (hereinafter abbreviated as FET) T1 to T6, the sources of Tl and T2 are commonly connected to the power supply 8, and the gate of T1 is is connected to the drain of T2, and T
The gate of T2 is connected to the drain of T1, the source of T3 is connected to the drain of T1, the gate of T3 is connected to the word line W, the drain of T3 is connected to the data line d, and the source of T4 is connected to the drain of T2. The gate of T4 is connected to the word line W, the drain of T4 is connected to the data line d, the source and gate of T5 are commonly connected to the drain of T1, and the source and gate of T6 are commonly connected to the drain of T1. T
The drain of T5 and the drain of T6 are commonly connected to the power supply VD. Further, the data lines d and d are connected to the power supply V through resistors Rs and 2, respectively.
Connected to DD. Note that in the memory cell, T
5. Since T6 operates as a load, replacing them with resistors does not essentially change the operation of the memory cell described here.

In FIG. 2, the memory cells constitute a flip-flop, and one of TI and T2 is kept in an on state, and the other is kept in an off state.

Here, to simplify the explanation, it is assumed that T1 is in the on state and T2 is in the off state. At this time, the drain of T1 is at low level and the drain of T2 is at high level. When the word line W is in a non-selected state (low level), T3. 'I'4 are both in the off state, and the potential of the data lines d and d is kept equal to the value of the power supply VDD. Here, VDD represents the power supply, the power line of the power supply, and the potential of the power supply. Commonly used for word line W
When becomes the selected state ()/I level), T3 changes to the on state and follows the path of ■DD-+R1 → d → T3 → T1,
A read current In flows. After a sufficient period of time has passed since the word line W changed to the selected state, the potential of the data line d drops to VDD Iyt-Rt. At this time, the potential of the data line d remains at VDD, so the line R-R1
A signal voltage with a magnitude of is transmitted to the sense amplifier. On the other hand, the time required for a sufficient signal voltage to appear on the data line can be considered as follows. data, 1jic
T3. There is a capacitance between the drain and gate of T4, a wiring capacitance, etc. Here, these capacitances are collectively expressed as cd and cd, as shown in FIG.

For simplicity, the time required for the word line W to change from the unselected state to the selected state is sufficiently short, and while the potential of the data line d is changing, the magnitude of the read current is as follows.
Assume that the constant value IR is ◎At this time, the potential of the data line d after the time when the word line W changes to the selected state is:
It changes over time as shown in Figure 3. The time constant of this potential change is given by Cd-R□, and the time required for the data line potential to change by half of the change to the final state is tn2×cd-几1; 0,69 XCd −Rt. (tn indicates the natural logarithm.) Therefore, in order to realize high-speed memory devices, CD-R1? : It is essential to make it small.

In general, in a semiconductor memory device, if the chip size and concentration level are given, the allowable memory cell size is approximately determined. Furthermore, since the thickness of the cell array is also determined, the capacitance cd of the data line is largely determined by the wiring capacitance determined from the device capacitance and the wiring width. Therefore, in order to increase the speed of the data line signal, it is necessary to reduce the load resistance R1k of the data line.

However, when trying to realize a very high-speed memory device, it is necessary to If r is made small, the wiring resistance of the data line becomes too large to be ignored, which becomes a problem.

For example, static
In a memory device, the access time can be reduced to less than 't 1 [IS], but in such a high-speed memory device, the time for the data line signal to change (0.69Cd-Rx as described above) is , for example, Q, is required to be short, 3 ns or less. In such a memory device, if the capacitance of the data line is, for example, IFF, then R1
must be approximately 400Ω or less. on the other hand,
For example, if the sheet resistance of the data line wiring is 0.1Ω, the wiring width is 2 μm, and the wiring length is IM, the wiring resistance of the data line is 50Ω. This is Rin! 10% of the size of
This is a size that cannot be ignored.

FIG. 4 shows one column extracted from the memory cell array of FIG. 1. In FIG. 4, memory cells M1 to Mn are connected to data lines d and d, and load resistors Rt and YL are connected to the ends of data lines d and d on the Mt side.
A power supply line VDD is connected through z, and a sense amplifier is connected to the end on the 60Mn side. In Figure 4,
d is one of dl, , dm in Fig. 1, d is d, , , d
m, R1 corresponds to one of R11 to fLm4, and R2 corresponds to one of R12 to R+m2. On the data lines d and d, the length tll from the point where the resistors & , Rz are connected to the point where the memory cell Ml is connected,
The length to the point where the memory cell Mn is connected is ftn,
Assuming that the length of each memory cell in the data line direction is kLmy, tn is longer than tl by (1) -+Rt→d→memory cell, so when reading the memory cell Ml, the wiring resistance rw1 due to tl, and when reading the memory cell Mn, the wiring resistance rw due to tn.
Each n becomes a problem. FIG. 5(a) schematically shows the current path when reading from the memory cell Ml, and FIG. 5(a) schematically shows the current path when reading from the memory cell Mn. Same figure (
As shown in a), when reading the memory cell Ml,
Read current IR is VDD-+R1→rw! →Since it flows through the path of the memory cell, the signal amplitude generated on the data line is I R·(Rt +rw+). On the other hand, the same figure (
As shown in b), when reading the memory cell Mn,
The read current IR is VDD-+几1-Jp r wn
→Since it flows through the path of the memory cell, the signal amplitude generated on the data line is IR·(几1+rwn). Therefore,
The amplitude of the read signal differs by IR·(rwn − rwl ) when reading the memory cell Ml in the first row and when reading the memory cell Mn in the nth row. Further, the time constant of change in data line potential when reading memory cell Mxk in the first row is Ccl ・(Rt +
rwt ), but the time constant when reading out the nth row memory cell Mn is cd·(R1+rwn). The fact that the reading speed of the data line signal differs depending on the position where the memory cell is connected to the data line becomes an obstacle in realizing a high-speed memory device.

[Purpose of the invention]

The present invention has been made to overcome the above drawbacks, and its purpose is to provide a semiconductor static type memory that reduces the influence of wiring resistance of data lines, increases circuit speed, and improves operational stability. The goal is to provide equipment.

[Summary of the invention]

To achieve this objective, the present invention arranges the power supply line and the load resistor within the memory cell array, and lengthens the data line from the point where the load resistor is connected to the point where the memory cell is connected. It is characterized by a small maximum value. As a result, the influence of the wiring resistance of the data line due to the connection position of the memory cell is reduced, and the speed of the read operation and the stability of the operation are improved accordingly.

[Embodiments of the invention]

FIG. 6 shows the configuration of an embodiment of the present invention, and this is an embodiment in which one load element is connected to each data line.

In this embodiment, the load resistance R11°R12~Rmt,
The configuration is the same as that of FIG. 1 except that Rmz and power supply line VDD are arranged within memory cell array CA. In this embodiment, the load resistance Rttr Rt2~
Rmt * mz (D is connected to each data line at approximately the center of the cell array CA, that is, at a position where n memory cells commonly connected to each data line are approximately equally grouped (approximately the midpoint of the data lines) In addition, the power supply line VDD is also arranged approximately at the center of the cell array CA in a direction perpendicular to the data line, and the load resistance Rtt r R12 to Rmt
+ Rmz is commonly connected. As a result, the influence of data line resistance is reduced to about one half compared to the conventional configuration shown in FIG. This means that on the data line, the maximum distance from the point where the load resistor is connected to the point where the memory cell is connected is approximately half of that in the configuration shown in Figure 1 in this configuration. Because it will be.

Although FIG. 6 shows an embodiment in which one load element is connected to each data line, an embodiment in which a plurality of load elements are connected will be shown next.

FIG. 7 shows the configuration of another embodiment of the present invention, and is an embodiment in which three load elements are connected to each data line. In the figure, Rxyl (X = 1~3°y = 1~m)
is the load resistance of the data line connected between the data line d and the power supply line VDD, Rxy2 (X = 1 to 3, y = l to m
) indicates the load resistance of the data line connected between the data line d and the power supply line VDD.The operation of the circuit shown in FIG. 7 will be explained using FIG. 8.

FIG. 8 shows one memory cell array CA from FIG.
This is a diagram showing the extracted columns. In Figure 8,
Memory cells Ml-Mn are connected to the differential lines d and d, a sense amplifier is connected to the M side end of the data line, and three load resistors, R11R211R, are connected to the data line d.
31 is connected, R111, R1211Rs1'J! !
: Intermediate, power supply VDD7>3 is connected, and data line d has three load resistors, R12 and R22.

R32 is connected, and the power supply line VDD is connected via R12e, R22, and R32. In Figure 8, d
is one of 61 to 6m in Fig. 7, d is one of 61 to 6m, and Rxt* R211R31 is 'BJ1nu1゜Rxmt m R211P'Rzm+ + R13, respectively.
11 to one of R3mt -Rt 21 R2z , R
a 2 is −respectively −Rxx2~Rrm2+R212~
It corresponds to one of R2mz + R312 to RI3 rr+z. On data lines d and d, load resistance R11, Rt
The length from the point where z is connected to the point where the first row memory cell Ml is connected is t,'' and the load resistance R2□.

From the point where R22 is connected, the load resistance R1t, R,t
Length k12'' to the point where □ is connected, load resistance RI3
．． .

From the point where R32 is connected, the load resistance R12111 (+
The length to the point where 22 is connected is A3'', the load resistance R3
The length from the point where 1m■3□ is connected to the point where the nth row memory cell Mn is connected is k14''. Also,
Wiring resistance of data lines corresponding to 11", A2", t, ", A4" e rWl" I rW2"l rW3/
/ I rW4〃O For simplicity, A1"= lz'= As"=t4"=
t.

R+tt=R12=R21=R24=Rsx
= R8223R, then -rWl""rW2"=
It can be written as rW3"::rW4":1. When reading the nth row memory cell Mn, the read current IF
, flows into the memory cell Mn from the data line d, the signal amplitude appearing at the point Nn where Mn is connected to d is -. ). In the configuration of FIG. 1, under the same assumption, the corresponding signal amplitude is approximately (R+r)IP, and in the configuration of FIG. 6, it is approximately (R+-)IF, so It can be seen that the configuration shown in the figure is effective in reducing the influence of wiring resistance.

In FIG. 7, the number of load resistors connected to the same data line is three, but even if the number of resistors is set to any number greater than or equal to two, the effects obtained by the present invention will be essentially different. do not have.

Note that in the above explanation, the load element connected to the data line is a resistor, but this can be replaced by a resistor with the same function,
For example, even if a FET with a gate and source connected is used, the effects obtained by the present invention will not essentially change. Also, the sense amplifier connected to the data line has both the signal amplification function and the data line pair selection function, but this uses something like a switch that has only the latter function. Even if there is, there is no change in the effects obtained by implementing the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the influence ψ caused by the wiring resistance of the data line due to the connection position of the memory cell is reduced, so it is possible to suppress the level fluctuation of the data line signal.
A memory device with higher speed and stable operation can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a part of a cell array and its peripheral parts of a conventional memory device, FIGS. 2 to 5 are diagrams for explaining the operation of FIG. 1 and its drawbacks, and FIGS. 7 is a diagram showing one embodiment of the present invention, and FIG. 8 is a diagram for explaining the operation of FIG. 7. M...Memory cell, CA...Memory cell array, W...Word m, WD...Word line driver%
VDn...power line, d, d...data line, R...
Load resistance, CD. CD...Common data line, SA...Sense amplifier, Atsushi j Figure χ? What Y33 Figure I4 Figure Kuzu 5 Figure ((1-) (J)) I 6th I 曾fh = Complete 7 Figure Wl Kaya 8 Figure

Claims (1)

[Claims] 1. A memory cell array in which a plurality of static memory cells are regularly arranged, and a plurality of the memory cells in a predetermined direction within this array are each commonly connected. a plurality of load elements, at least one of which is connected to each of the data lines in the memory cell array; and a plurality of load elements connected to the plurality of load elements and arranged in the predetermined direction. and at least one power supply line extending in a direction substantially perpendicular to the static memory device. 2. The load element is connected to each of the data lines at a position that substantially equally groups the plurality of memory cells commonly connected to each of the data lines. A static memory device according to scope 1. 3. A plurality of the load elements are connected to each of the data lines at different positions, and the power supply line has a plurality of load elements connected to each of the data lines at different positions. A static memory device according to claim 1, characterized in that the static memory device comprises a power supply line. 4. The plurality of load elements connected to each of the data lines are connected at positions that substantially equally group the plurality of memory cells commonly connected to the data line. A static memory device according to claim 3.