JPS5951635A - Pilot signal eliminating circuit - Google Patents

Abstract

PURPOSE:To improve the pilot signal eliminating characteristic, by applying a composite signal and a signal converting the waveform of a rectangular wave signal having the same frequency as that of a pilot signal to a non-inverting and an inverting input terminal of an operation processing circuit. CONSTITUTION:The composite signal of an FM stereo broadcast inputted to a terminal 15 passes through a buffer 16, then it is inputted to the non-inverting input of the operation processing circuit 17 and to a phase detector 25. An output signal of the detector 25 is inputted to a PLL circuit consisting of an LPF26, a DC amplifier 27, a voltage control oscillator 28, and frequency dividers 29, 30, and an output of the frequency divider 30 is inputted to a phase detector 24 through a frequency divider 31 generating a rectangular wave of a pilot PL signal frequency having different phase from the output of th frequency divider 30 by 90 deg.. An output of the circuit 17 is inputted to a decoder 18 separating an L and an R signal, the phase detection is attained with a rectangular wave from the frequency divider 31 by the detector 24, a converting signal synchronized with the PL signal is outputted from a waveform converter 21 and inputted to an inverting input of the circuit 17. Thus, a signal eliminated with the PL signal is obtained from the circuit 17.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an FM stereo broadcast receiver.

In particular, regarding the circuit for removing the pilot signal contained in the composite signal, for more details, please refer to the pilot signal (1
Regarding a pilot signal removal circuit that can be directly connected to an arithmetic processing circuit for removing 9k)lz) [Description of Prior Art] FIG. 1 is a block diagram of a conventional pilot signal removal circuit.

In the same figure, this circuit
Mixed signal including 9k liz pilot signal. same as below. ) input terminal 1, buffer amplifier 2, preamplifier 3, phase waveform generator 4, low-pass filter 5, and linear ξ
The amplifier 6 includes a voltage controlled oscillator 7, a frequency divider 8.9, an adder 10, and a waveform converter 12.

The composite signal from input terminal 1 is sent to buffer amplifier 2.
The DC component is applied to the adder 10 after being blocked by the capacitor C1. On the other hand, the composite signal input to the preamplifier 3 is input to a PLL circuit (phase locked circuit) consisting of a phase detector 4, a low-pass filter 5, a DC amplifier 6, a voltage controlled oscillator 7, and a frequency divider 8.9. However, by this PLL circuit, a rectangular wave output synchronized with the pilot signal is obtained by the frequency divider 9, and the rectangular wave output from the frequency divider 9 passes through the waveform converter 12, and its DC component is sent to the capacitor C2.
After being cut off at , it is applied to the adder 10 .

As a result, the pilot signal is removed from the output of the adder 10, and this output is further passed through the decoder 11 and separated into an L signal and an R signal.

In this conventional circuit, an adder 10 and a waveform converter 12
is not included in the feedback loop, relatively large capacitance DC blocking capacitors C1 and C2 are required to remove the pilot signal. For this reason, conventional circuits have the disadvantage of causing deterioration of the pilot signal rejection characteristics, and also have the disadvantage of increasing the number of terminals of the semiconductor integrated circuit because it is necessary to connect a capacitor outside the semiconductor integrated circuit. .

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks and provides a pilot signal removal circuit that has a circuit configuration that can be directly connected to an arithmetic processing circuit, thereby improving deterioration characteristics and reducing the number of terminals when integrated into a semiconductor circuit. The purpose is to provide.

[Key points of the invention]

The present invention relates to a circuit that generates a rectangular wave signal having the same frequency as the pyro and gating signals of a composite signal in FM stereo broadcasting, a circuit that converts the waveform of this rectangular wave signal, and an output of the composite signal and the waveform conversion circuit. and an arithmetic processing circuit which inputs the signals to the positive phase input terminal and the negative phase input terminal, respectively, and obtains a signal from which the pilot signal is removed from the output of the arithmetic processing circuit. The present invention is characterized in that when the pilot signal is removed from the output of the circuit, the potential becomes equal to the potential of the negative phase input terminal of the arithmetic processing circuit.

[Explanation based on examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of a circuit according to an embodiment of the present invention.

In the figure, the composite signal is input to the input terminal 15, passes through the buffer amplifier 16, and passes through the arithmetic processing circuit 17.
The signal is input directly to the positive phase input terminal of , and is also input to the phase detector 25 .

The composite node signal input to the phase detector 25 is passed through a low-pass filter 26, a DC amplifier 27, and a voltage-controlled oscillator 2.
8. It is input to the PLL circuit composed of frequency dividers 29 and 30, and the rectangular wave output of frequency divider 30 has a phase of approximately 9 with this output.
Frequency divider 3 that generates 19 kHz square waves differing by 0°
1 and is input to the phase detector 24.

The output of the arithmetic processing circuit 17 is led to a decoder 18 that separates the L signal and the R signal, is input to the phase detector 24, passes through a low-pass filter 23, a DC amplifier 22, a waveform converter 21, and is subjected to arithmetic processing. It is input to the negative phase input terminal of the circuit 17. The output of the two PLL circuits is guided to the waveform converter 21 as a synchronizing signal for waveform conversion, and outputs a waveform-converted wave having an amplitude corresponding to the output of the phase detector 24.

When the circuit is configured as described above, the output of the arithmetic processing circuit 17 is transmitted to the frequency divider 31 at 19 kHz by the phase detector 24.
Phase detection is performed using a rectangular wave, and the output of the waveform converter 21 is a converted wave that changes in amplitude corresponding to the detected output of the phase detector 24 and is synchronized with the pilot signal.

Therefore, a composite signal is applied to the positive phase input terminal of the arithmetic processing circuit 17, and a waveform synchronized with the pilot signal in the composite signal is applied to the negative phase input terminal. The waveform converter 21 is included in the feedback loop of the arithmetic processing circuit 17, and its output is automatically adjusted to a value such that the pilot signal is removed from the output of the arithmetic processing circuit 17. Therefore, a signal from which the pilot signal is removed can be obtained as the output of the arithmetic processing circuit 17. This signal is further separated into an L signal and an R48 signal via a decoder 18.

In this circuit configuration, the waveform converter 21 is connected to the arithmetic processing circuit 17.
Since the configuration enters a feedback loop through
does not require. In this way, the DC cutoff capacitor C1,
Since C2 is not required, pilot signal removal characteristics can be improved.

FIG. 3 is a circuit diagram of a more specific embodiment of the present invention.

In the figure, this circuit includes a buffer amplifier 32, an arithmetic processing circuit 33, a waveform converter 34, a phase detector 37, and a DC amplifier 3B. 36 is an output terminal for a waveform-converted wave, 39 is an output terminal for a signal from which a pilot signal has been removed, and 40.41 is a synchronization signal input terminal. The buffer amplifier 32, the arithmetic processing circuit 33, and the waveform converter 34 are directly connected to each other, and a waveform synchronized with the pilot signal in the composite signal is generated at the output terminal. The buffer amplifier 32, arithmetic processing circuit 33, and waveform converter 34 have a circuit configuration suitable for semiconductor integration.

[Explanation of effects]

As explained above, the present invention enables direct connection to the arithmetic processing circuit without using a capacitor, eliminating the need for an external capacitor, thereby improving pilot signal rejection characteristics. It is possible to reduce the number of terminals when fabricating a semiconductor integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional pilot signal removal circuit. FIG. 2 is a block diagram of an embodiment of the pilot signal removal circuit of the present invention. FIG. 3 is a circuit diagram of a more specific embodiment of the present invention.

Claims (1)

[Claims] (1) A generation circuit that generates an output signal with the same frequency as the pilot signal from a composite signal including the pilot signal, input terminals for positive phase and negative phase, and an output terminal from which a signal from which the pilot signal has been removed is output. a differential arithmetic circuit having one input terminal to which the above-mentioned combo shift) signal is input; a detection circuit for phase-detecting the output of the differential arithmetic circuit with the output of the above-mentioned generation circuit; A pilot signal removal circuit for an FM stereo receiver, comprising a waveform conversion circuit that changes the amplitude of the waveform conversion wave in accordance with the output of the detection circuit and sends the waveform converted wave to the other input terminal of the differential calculation circuit.