JPS5956189A - Frequency adjusting circuit of electronic timepiece - Google Patents

Abstract

PURPOSE:To decrease the number of pins of an IC by reading the frequency division ratio of a programmable frequency divider externally as serial data, and converting this serial data into parallel data and setting it as the frequency division ratio in the programmable frequency divider. CONSTITUTION:An input reading circuit 16 inputs a serial signal TP indicating the frequency division ratio of a programmable frequency dividing circuit 2c and a clock signal CL and they are stored as parallel data in a frequency division ratio storage circuit 14. The data in the frequency division ratio storage circuit 14 is written in a nonvolatile memory in the programmable frequency dividing circuit 2c, setting the frequency division ratio by the memory.

Description

[Detailed Description of the Invention] The present invention is an electronic! Regarding the improvement of the frequency adjustment method of the 13-meter, in particular, the frequency division ratio of the 6 frequency divider used in electronic watches can be set externally using serial data instead of parallel data, and the number of terminals of the IC bin for the watch has been improved. This is a significant reduction in

Traditionally, adjusting the reference frequency signal for time display was done by varying the capacitance of the trimmer capacitor of the reference signal generator, but in recent years it has become possible to adjust the frequency more accurately and more easily. Therefore, it has been considered to change the frequency division ratio of the 6-frequency divider instead of dividing the signal from the reference signal generator. FIG. 1 shows its circuit diagram.

2 is a programmable frequency divider that divides the reference signal from the reference signal generator 4 by a desired frequency block, and a frequency dividing circuit 2a
, 2b, and a programmable frequency dividing circuit 2C2. The frequency division ratio of the programmable frequency divider circuit 2C is written in parallel data based on the opening and closing of individual switches in the switch group 60, and is set by the non-volatile memory 6.

The signal from the programmable frequency divider 2 is sent to a waveform shaping circuit 8.
The signal is converted into a pulse signal via the buffer 10 to drive the motor 12.

According to the above-mentioned method, the time display frequency can be adjusted more accurately than the method in which the oscillation frequency of the reference signal generator 4 is varied using a trimmer capacitor. Otsu can be said to be otsu.

However, if this clock circuit is integrated, the switch group 6 must be externally attached. In this case, the number of pins in the integrated circuit is large, and the number of pins increases, resulting in restrictions such as Hanokage, which also leads to higher costs.

The present invention has been devised in view of the conventional problems mentioned in section 2, and it is possible to integrate the frequency adjustment without sacrificing the accuracy of frequency adjustment by the conventional method of setting the frequency division ratio of the frequency divider using parallel data. The purpose is to significantly reduce the number of pins in the circuit.

In order to achieve all of the above objects, the present invention reads the division ratio of a programmable frequency divider from outside as serial data, reads this serial data into a total division ratio storage circuit, converts it into parallel data, and converts the serial data into parallel data. The feature is that the frequency division ratio is set in the programmable frequency divider.

The present invention will be described in detail below based on the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

Components having the same configuration as those in FIG. 1 are given the same numbers and will not be fully described.

The programmable frequency divider circuit 2C includes a frequency division ratio storage circuit 14.
The Q output signals of the eight FF groups 14a to 14h making up the circuit are input. This frequency division ratio storage circuit 14 is a storage 1-B circuit that converts serial data supplied from the outside for shifting the frequency division ratio setting of the programmable frequency division circuit 2c into parallel data.

Frequency division ratio storage circuit 14'f configuration 1-B FF group 14a to 14
The external clock signal CL is input to the clock input φ of h.
is input, reset human power R and first FF14
A signal from the manual reading circuit 16 is input to the D input of a.

The input reading circuit 16 is an initial reset circuit 18°FF2.
0, octal counter 22. It is composed of Orkate 24° and Gate 26, 28.30.

A 1-7 real signal TI) representing the frequency division ratio data of the programmer full frequency divider circuit 2c is input to the input of the FF20, and this serial signal TI) is also input manually to the frequency divider circuit 26. , 1 I/I/20υ) The output 30a of the AND gate 30 is input to the clock input φ,
An external clock (g' Q
The Q output 20b of CL and FF20 is manually operated. F
The Q output 20a of the F20 is input to the Antoge River 26, and the output 20b is the reset input R of the octal counter 22.
It is man-powered.

And the output 26a of ANDKATE 26 is D of FF14a.
Input is done manually.

Also, the Q output 20a of the FF 20 is input to an AND gate 28, and this AND gate 28 is connected to other external devices.

The clock signal CL from these is input. The output 28a of this Antogame 1.28 is input to the clock φ of the octal counter 22.
It is input to the aH orate 24, and the output 24a of this orate 24 is inputted to the reset manual power R of the FF 20.

On the other hand, the output 18a of the initial reset circuit 18 is input to the reset input R of the FF groups 14a to 14h of the frequency division ratio setting circuit 14 and the ORKATE 24.

The operation of this circuit will be explained below using the time chart shown in FIG.

When the power supply battery (not shown) is fully turned on, a positive single pulse is obtained at the output 18a of the initial reset circuit 18, and F
F group 14a to 14h and F'F20 temporary reset state and 1-B.

After this, from the outside, the time chart in Figure 3 shows '1''.
As shown in FIG. The division ratio data of "HHHIILHLHJ" is displayed, and the serial signal TP
The first pulse is a trigger pulse, not the frequency division ratio data. , Therefore, when the first pulse of the serial signal TP rises and then the first pulse of the clock signal CL rises, the FF2(1) Q output 20a becomes "■1
", Q output 20b is II, J. As a result, the AND gates 26 and 28 are opened, and a pulse signal having the same phase as the output 26 a Vo:i' real signal TP is obtained, and the output horn 2
8a is a pulse signal in phase with the clock signal CL;
It's late. The pulse signal obtained at this output 26a is FF1
It is supplied to the D input of 4a. And this output 26a F
The phase is advanced compared to the clock signal CL input to the F groups 14a to 14h, and therefore the RIO/RI signal CI
When the second pulse of J rises, FF groups 14a to 14h
The Q output of FF group 14a-14h becomes rIILLLLLLJ, and when the third pulse rises, the Q output of FF group 14a-14h becomes rL
HLLLLLLL'J. Thereafter, each time the clock signal CL rises, rHLHLLLLLJ, rLHLHLLL
L J, r HL HL HL LL J
, . . . and becomes r HHHHL ) (LHJ at the rising edge of the final ninth pulse.

On the other hand, the pulse signal of the output 28a is counted by the octal counter 22, and when the ninth pulse rises, it rises to the output 22 a B r HJ of the octal counter 22.

As a result, the Q output of FF20 is 20a kerl, J is 2
0b is reversed to rJ, and AND gates 26 and 28 are closed.

As a result of this operation, parallel data rHHHI(LHLT(J), which is the same as the serial signal TP, is set and stored in the FF groups 14a to 14hK, and this data is written to the nonvolatile memory in the programmable frequency divider circuit 2c. The division ratio is set by the memory.

As described above, according to this embodiment, by inputting the frequency division ratio data of the programmable frequency dividing circuit 2c from the outside as a 7real signal, the integration can be significantly increased compared to conventional inputs from the outside as a parallel signal. How many pins in the circuit? Since there are no packaging restrictions, this leads to cost reductions.

In this first example, the frequency division data of the programmable frequency divider circuit 2c is 8 bits, but the programmable frequency divider circuit 2c
Bit I71 can be changed according to the number of frequency division stages of c. .

As described above, according to the present invention, in the same lesson in which the frequency of II word 1 is adjusted by fully varying the frequency division ratio of the programmable frequency divider, the frequency division ratio is fully set to '1'.
By inputting and reading the frequency division ratio data from the outside as a serial signal instead of a parallel signal, converting it to a parallel signal and storing it, all frequency division ratio settings are set to 1. -The number of integrated circuit bins required for 1-manpower operation can be significantly reduced.
This results in a significant cost reduction.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example. FIG. 2 is a circuit diagram showing one embodiment of the present invention. FIG. 3 is a time chart in FIG. 2. 2. Programmable frequency divider, 4. Basic thread signal generator, 14. Frequency division ratio storage circuit, 1
6. Input reading circuit. that's all

Claims (1)

[Claims] (1) In an electronic watch that includes a reference signal generator that generates a time reference signal and a frequency divider that divides the frequency of the time reference signal to a desired frequency, It consists of a programmable frequency divider that can be set, a frequency division ratio storage circuit that converts and stores all the frequency division ratios set in the programmable frequency divider into parallel data, and a frequency division ratio storage circuit that converts and stores the frequency division ratio set in the programmable frequency divider into parallel data, and a frequency division ratio storage circuit that converts and stores serial data from outside to the frequency division ratio storage circuit. 1. A frequency adjustment circuit for an electronic watch, comprising: an input reading circuit for reading a ratio.