JPS5956760U - semiconductor integrated circuit - Google Patents

semiconductor integrated circuit

Info

Publication number
JPS5956760U
JPS5956760U JP15197682U JP15197682U JPS5956760U JP S5956760 U JPS5956760 U JP S5956760U JP 15197682 U JP15197682 U JP 15197682U JP 15197682 U JP15197682 U JP 15197682U JP S5956760 U JPS5956760 U JP S5956760U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
wiring pattern
deleted
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15197682U
Other languages
Japanese (ja)
Inventor
木本 学
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15197682U priority Critical patent/JPS5956760U/en
Publication of JPS5956760U publication Critical patent/JPS5956760U/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はそれぞれ本考案の実施例を示す平面図
である。 10.20・・・・・・共通電源線(高電位電源線及び
低電位電源線)、11.12・・・・・・抵抗素子、2
1゜22・・・・・・MOS  FET、13.23・
・・・・・ポンディングパッド、24・・・・・・ゲー
ト電極線。
FIGS. 1 and 2 are plan views showing embodiments of the present invention, respectively. 10.20... Common power line (high potential power line and low potential power line), 11.12... Resistance element, 2
1゜22...MOS FET, 13.23・
. . . Bonding pad, 24 . . . Gate electrode line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1つの共通電源線と入力もしぐは出力端子間に複数個の
抵抗素子もしくは能動素子が配線パター□  ンによっ
て結ばれ、任意に並列・直列または開放接続できるよう
に配線パターン内の1部の領域にあらかじめ配線パター
ンを削除しうる部分を設けであることを特徴とする半導
体集積回路。   ゛
Multiple resistive elements or active elements are connected between one common power supply line and input or output terminals by a wiring pattern, and some areas within the wiring pattern are connected so that they can be connected in parallel, in series, or open as desired. A semiconductor integrated circuit characterized in that a portion from which a wiring pattern can be deleted is provided in advance.゛
JP15197682U 1982-10-06 1982-10-06 semiconductor integrated circuit Pending JPS5956760U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15197682U JPS5956760U (en) 1982-10-06 1982-10-06 semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15197682U JPS5956760U (en) 1982-10-06 1982-10-06 semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5956760U true JPS5956760U (en) 1984-04-13

Family

ID=30336627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15197682U Pending JPS5956760U (en) 1982-10-06 1982-10-06 semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5956760U (en)

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