JPS5956826U - gain adjustment device - Google Patents
gain adjustment deviceInfo
- Publication number
- JPS5956826U JPS5956826U JP14954382U JP14954382U JPS5956826U JP S5956826 U JPS5956826 U JP S5956826U JP 14954382 U JP14954382 U JP 14954382U JP 14954382 U JP14954382 U JP 14954382U JP S5956826 U JPS5956826 U JP S5956826U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- adjustment device
- gain adjustment
- collector
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Networks Using Active Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案による利得調整装置の回路図、第２図
は同装置の可変抵抗器を調整することによ −
り周波数特性が変化する状態を示した図である。
２・・・・・・トランジスタ、１２． １４． １８．
２４・・・・・・バイアス回路、３６・・・・・・負
荷回路、５０・・・・・・帰還回路。 −Figure 1 is a circuit diagram of a gain adjustment device according to this invention, and Figure 2 is a circuit diagram of a gain adjustment device according to this invention.
FIG. 3 is a diagram showing a state in which the frequency characteristics change. 2...transistor, 12. 14. 18.
24...Bias circuit, 36...Load circuit, 50...Feedback circuit. −
Claims (1)
アス回路を設け、上記トランジスタのコレクタと動作電
位点との間に負荷回路を接続し、上記ベースとコレクタ
との間に帰還回路を設け、この帰還回路内に直列に介在
する可変抵抗器の両端間にコンデンサとりアクドルとの
直列回路を接続し、このコンデンサとりアクドルとの接
続点に上記可変抵抗器の腕を接続してなる利得調整装置
。A bias circuit is provided at the base and emitter of the high frequency amplification transistor, a load circuit is connected between the collector of the transistor and the operating potential point, a feedback circuit is provided between the base and the collector, and a series circuit is connected within this feedback circuit. A gain adjustment device is constructed by connecting a series circuit with a capacitor and an axle between both ends of a variable resistor interposed therein, and connecting an arm of the variable resistor to a connection point between the capacitor and the axle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14954382U JPS5956826U (en) | 1982-09-30 | 1982-09-30 | gain adjustment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14954382U JPS5956826U (en) | 1982-09-30 | 1982-09-30 | gain adjustment device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5956826U true JPS5956826U (en) | 1984-04-13 |
| JPH0122263Y2 JPH0122263Y2 (en) | 1989-06-30 |
Family
ID=30331931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14954382U Granted JPS5956826U (en) | 1982-09-30 | 1982-09-30 | gain adjustment device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5956826U (en) |
-
1982
- 1982-09-30 JP JP14954382U patent/JPS5956826U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0122263Y2 (en) | 1989-06-30 |
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