JPS5960491A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a display device that uses all of the display elements such as light emitting diode, and particularly to a display device that uses all of the display elements such as light emitting diode, and in particular, a display device that displays television images on a large screen by connecting a series of small unit display devices vil. The present invention relates to a display device for displaying images. It is something.

[Technical background of the invention and its problems]

A display/ray device consisting of a matrix array of display elements such as light emitting diodes (LEDs) can be made smaller and thinner than a display/ray device using a cathode ray tube, and can operate at low voltage. 1mxl in history? It is effective in that it can create a screen area as large as that of i'.

Conventionally, as a driving method for such a Tisgelley device in which all display elements are arranged in a matrix, a line sequential scanning method, which is a composite method that takes advantage of the advantages of both a dynamic method and a static method, has been used. This method can be easily implemented by converting the drive signals given to the row lines of the display element array into time schedules and driving the row lines in a sequential scan manner.
In synchronization with this, all binary level image data (1/1" or !lol+) is selectively switched to the column line.

However, in this line sequential scanning method, for example, the 64x64 multicolor LED display device described in "Electronic Materials J February 1980 issue P68-P72,"
IEFJT Sosuda SAC'i"ION ON ELECT
RONDEVICES J VOL, ED-26,
Bian 68, AUGUST 1979゜P1182-1
186) 7. 96x64 pixels.

As seen in 160 x 12 pixel television scanning matrix display devices, as the screen size or number of pixels increases, the external device that drives this glazed display device (the image data processing speed of the device) increases. Due to the limitations, it is difficult to scan at a repetition frequency that does not cause flickering to the human eye.Also, the current that momentarily flows through the display element play is determined by the number of pixel data given to the column line. Because a large current flows through the wire,
The advantages of this type of flat display device, such as miniaturization and compatibility with IC, are lost. Furthermore, it is disadvantageous in terms of increasing the overall brightness of the display.

Therefore, in the past, when producing a large-screen Tisgelley device with an extremely large number of pixels, for example, rcONFERE was used.
NcE RECORD OF 1978 BIENNI
ALDISPLAY RESEACHC0NFEF,E
NCE J 0CTOBER24~26.197B, 5
FLAT-PANEL DI described in IDP20-21
A method has been considered in which a large number of small unit Nice Play devices each having a 1M circuit on the back side of the board are connected, such as SPLAY. The drive circuit attached to the above-mentioned unit display device is provided with a number of memory elements corresponding to the number of pixels of the display element array of this unit display device, and each unit has a frequency of * f, ! The display element array in the display element array is one that can be driven independently, and is suitable for the 11 responses of the LEDs mentioned above, and it can be easily integrated into an IC.

A large-scale display device constructed by connecting such small-sized unit display devices to form a large screen yk can be schematically represented as shown in FIG. That is, 1 is an LED array as an indicator of a plurality of LEDs arranged in a matrix with a monolithic or hybrid structure and a predetermined pixel number on a substrate, and 2 is a drive for driving this LED array 1 by the line sequential scanning method. A unit display device 3 is a module driver as a circuit that is completely integrated with an LED array 1 and a module driver 2 to have a display function independently. Then, this unit Tisgerei device 3 is arranged in a matrix array with 1111 sides of the desired size.
It is the unit driver 5 that supplies various signals and electric cooling 2 to the panel 4, and these are the unit panel 4 and unit driver 5? A unit 6 that is combined and has one display function as a whole becomes the heat unit 6.

The inventors have already proposed a specific method for constructing the above-mentioned unit display device, particularly the module driver therein (Japanese Patent Application No. 57-20113). This basic column configuration uses an m×n stage static shift register for the number of pixels m and n in each row and column direction of a matrix-arranged display element array as a storage circuit for both image data.
The output of the first m stages drives the display element array (σ) column line, and the image data is input to the shift register or the shift register is inputted from the outside depending on the level of the select signal ty>2 (in level). The cyclic operation is switched in seven steps. On the other hand, the row lines of the display element array are scanned and driven based on the count of clock signals.

By doing so, the circuit configuration of the module driver included in the unitary device can be simplified. This f'L mainly stores the image data 'lil'*1j'i to be supplied to the display element play.The memory circuit is composed of a shift register, and only the input cut of the shift register and the shift operation by the clock signal are performed. This is a method that can take in and read out 7 pixel signals.Therefore, it is possible to reduce the power consumption of the module driver, and when converting this module Drino into an IC, this f'L' is used as the display element array. It is easy to install it at the bottom of the board where it is arranged.

Furthermore, such a display device is arranged in a matrix as a unit display device to form a large screen display device (display unit) as a unit panel.
When configuring, select signal lines and clock signal lines are arranged in the row and column direction of all units and panels,
By controlling the drive of each of the 4 unit tinurray devices as a whole in the same manner as in sequential scanning, the combination of the select signal and the clock signal is controlled by the supply pattern of the select signal and clock signal from the unit driver to these lines. Since the unit Niceplay device can be controlled, the number of wiring between the unit driver and the individual unit display devices is significantly reduced, and the configuration of the unit driver is also simpler. Therefore, it is possible to relatively easily realize an extremely large screen having several hundred unit display devices.

By the way, such a large screen area? Information sources for image data for display devices include various terminal devices such as computers and TV multiplier signals9, but image data cannot be scanned by a computer. The television scanning system is advantageous because it requires a huge amount of memory to store a large amount of information, all with relatively simple circuitry. JQ1Usually, when giving a television image signal t″1″ or t″10″ as a binary signal to a display device, the NTSC (Nat+bn
n I'l'elevl 5ion System
Ca7. In the ttie) method, image signals are processed using 52" horizontal synchronization signals per frame and 92 vertical synchronization signals per frame. In this case, image signals within the horizontal synchronization period This problem can be solved by sampling at sampling intervals divided by the number of pixels in the horizontal direction of the display device, so it is not limited to the number of pixels in the horizontal direction of the display device, but the number of pixels in the vertical direction is Therefore, the number of pixels in the vertical direction is 2625.
For display devices that exceed the number of horizontal scanning lines of a book, either multiple horizontal pixel rows are scanned all at once, or they are created using the video circuit of a television receiver, as in the case of computer scanning described above. This requires complex image processing, such as storing the refined image signal in memory, processing all the data, and outputting it in accordance with the number of pixels arranged vertically. This determines the effective picture size for displaying television images on a display device using the above-mentioned display element array. In other words, the number of pixels in the vertical direction is 262, which is the number of horizontal scanning lines per field.
．． 5 or less, and regular television iIl! 1
The width to height ratio of one screen is 4:3, and the width is 320. It can be seen that 240 vertical pixels is the ideal maximum number of pixels.

However, since a unit display device configured with a specific number of pixels operates independently, if a display device with a large screen area is constructed by simply connecting these unit display groups #, the image It becomes difficult to match display timing, brightness balance, etc. without any problems.

That is, the image signal once stored in the shift register in the unit display device is circulated and output when the select signal commonly given to the unit display group R (unit row) lined up in 411N traps is not selected. It has become. This display operation is performed by clock signals commonly given to unit display groups R (unit rows) arranged vertically, so that the counter rotates with the movement of the shift register. If the next vertical synchronization signal appears before the signal is input and scanning of a new 1 dil image signal begins, the internal counter will malfunction and a correct image cannot be produced. Also, nxN horizontal scans to prevent this? If the clock signal is stopped so that the horizontal synchronization signal is not output until the vertical synchronization signal appears after completion, the clock signal is stopped.
During this time, the counters in the n unit display devices are stopped at the n-th display, and display operations are performed for a long time compared to other scanning lines, resulting in problems such as brightness being different and good image quality not being obtained.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a large-screen unit display device which is constructed by combining a large number of unit display devices each having a specific number of pixels and is capable of correctly displaying a large-screen unit image.

[Summary of the invention]

The display device according to the present invention has a specific number of pixels m.
A display element array formed by connecting t matrix of display elements of Xn, a shift register having the same number of stages as the number of pixels (mxn) of this display element array, and a shift register operated by a clock signal from the outside, and a select signal and an image from the outside. A switching circuit that receives data, inputs the image data to the shift register from the first stage when the select signal is at the first level, and inputs the output of the final stage of the shift register to the first stage when the select signal is at the second level. and nil
ii) means for current amplifying the output of the first m stages of the Q shift register and supplying it to the column line of the display and child array;
Means for sequentially selecting the row lines of the display element array as soon as m lock signals are input; and selecting operation of the row lines based on an external brightness adjustment signal 'f: a brightness adjustment signal to be prohibited; The unit tisgelei device containing all the power t't N
The first unit is composed of units or panels connected in rows and M columns, and a unit driver that drives the unit (e) to display a television image.

The unit driver includes a means for binarizing valid image data of the horizontal synchronization signal of the television image signal and providing it in common to the @Oki No. 1 Nice Play devices of the unit panel; A clock that starts when vertical and horizontal synchronization signals are applied at the same time, and repeats the output operation of IlNlN power by clock signals fm to each column of the unit panel each time a horizontal synchronization signal arrives with a sufficient pause period. Signal generating means and mXr1 applied to all columns of said unit panel by this means.
a select code generating means for sequentially outputting all select signals to each row of the unit panel at the timing of a horizontal peer signal each time a clock signal is outputted one by one; brightness adjustment signal generating means for outputting all common brightness adjustment signals;
Means is provided for stopping the output of all Jl1 clock signals of the unit panel by the clock signal and the select signal, and at the same time superimposing a display blanking pulse on the output of the previous nQ brightness adjustment signal generating means.

That is, according to the present invention, the effective image data A' within the period of the horizontal periodic signal given to the number of pixels mXM lined up horizontally on the unit panel is sampled while switching M times in units of the number of clocks m. Ru.

This operation is performed by first connecting the vertical and horizontal television image signals simultaneously, and then the select signal is given to the first unit row.
The rows are selected. Furthermore, the second line in the next horizontal direction - period issue,
It switches to the third line and so on, and scans n lines. When the front of n rows is completed, the horizontal synchronization signal switches the image sequence and at the same time the select signal for selecting the unit column is transferred to the second unit column and scans this 8 times one after another, and then the vertical plane of the arrow is When the synchronization signal appears (/), the image data within the 6262.5 horizontal synchronization signals is analyzed for each unit. At this time, the number of pixels in the vertical direction of the unit panel is nxN (262.5 pixels), each of which is a positive number that does not exceed the total number of pixels. If you choose , the horizontal synchronization signal of 0.5 or more will be odd. Therefore, during the period 1 when the next vertical synchronization signal appears after all nXN horizontal scans are completed, a Plankink pulse is generated that stops all clock signals and at the same time completely prohibits display operations, and the unit panel It is applied to the brightness adjustment circuit of each unit display device for drive control.

〔Effect of the invention〕

According to the present invention, if the number of times to scan the product n×N of the number of vertical pixels of a unit display device and the number of vertical unit columns N is a number n that does not exceed the number of horizontal synchronization signals, then Television images can be created using a simple image processing circuit.

Furthermore, even in a gray unit that combines a large number of unit display devices that can be displayed instantly, television images can be projected without completely adjusting the balance of the image and brightness.

[Embodiments of the invention]

2 to 4 show the configuration of a unit display device according to the present invention and its time chart. The LED array 1 as a display element array is m (row direction) x n (
(column direction) LEDs t=arrayed in matrix, n
It is connected to each intersection of a row line and n column lines of a book. Here, the value of mkn is, for example, m=n-16.

The LED array 1 is configured, for example, on one substrate. A module driver 2 for driving the LED array 1 is provided at the bottom of this board. These two module drivers are configured as follows.

In other words, the module driver 2 receives a select signal S, serial image data D1, a clock signal C1, and a reset signal R.
1 brightness modulation signal B1 enable signal E is input from the outside. Among these signals, select signal S1 serial i image data D is 1. Static D gate 11, inverter 1
2, n obtained by a configuration such as an AND gate 13 and an OR gate 14, is input to the switching circuit 10.

In this switching circuit 10, the level of the select signal S is 5=11.
11', the image data Di is input to the shift register 15 from the first stage, and when tfcs="o", the output of the final stage of the shift register 15 is input to the first stage.

The shift register 1.5f is a static shift register with mXn stages, in other words, it is composed of n blocks B1-13n, with all m stages as one block. The outputs of the first block B1% of this shift register 15, that is, the outputs from the first stage to the mth stage, are converted to L
It is given to the row line in ED array 1.

On the other hand, the clock signal C is applied to the shift register 15 and is also input to the bit counter 2. The bit counter 21 and the address reference counter 22 are set to an initial state by a reset signal R, and output a carry signal CA every time m=16' of the clock signal C is counted. Note that the clock signal C is −m +
There is a period of 10 to 1,004 pauses between the first one and the first one. Address counter 22 receives this carry signal CA' and sequentially outputs address signals specifying column lines in LED array IVC to decoder 17.

There is also an AND gate 31 within the unit display fabrication.
A brightness adjustment circuit 30 constituted by 32 and an OR gate 33 is provided, and an enable signal E for controlling all brightness adjustment operations based on the brightness adjustment signal B is provided. In this case, the brightness adjustment signal B
Then, a pulse wave signal whose width can be arbitrarily modulated between 1 and 15 cycles of the n clock signal given during the above-mentioned rest period is used for each clock signal C (/, lm=16). It will be done.

The time chart in FIG. 4 shows the situation.

This brightness adjustment signal B is input to the first eyebrow gate 31.
b. On the other hand, the bit counter 21 determines that A, B, C, D.
A carry signal CA, which becomes low level when all the outputs are high level, is output and input to the second gate 32 and the address counter 22. Brightness adjustment signal B and carry signal CA are AN when enable signal E is high level.
It passes through the D gates 31 and 32 and is formed at the OR gate 33 to become the n1 brightness enable signal BE. This brightness enable signal BE is applied to the decoder 17, and when BE is at a high level, the scanning signal output from the decoder is completely inhibited and the lighting operation of the LED array 1 is stopped. This stop time corresponds to the pulse width of the brightness adjustment signal B, and therefore, the display brightness of the LED array 1 can be completely adjusted according to this pulse width. Note that when the enable signal E is at a low level, the brightness adjustment signal B and the carry signal CA are ignored by the brightness adjustment circuit 30, so that no brightness adjustment is performed.

The unit panel 4 in FIG. 5 is the unit display device Wt or 3k in FIG. 2 arranged in a matrix on, for example, a single printed circuit board.

Here, the number of rows arranged in the unit display device 3 is assumed to be N, the number of rows arranged in M1 columns. However, in Fig. 5, there is a difference between Fig. 3 and Fig. 3.
The horizontal direction is the row, and the vertical direction is the tone sequence. This unit panel 4 receives image data D, a reset signal R1, a brightness adjustment signal B1, an enable signal E, which are commonly given to all the unit display devices 3 from the unit driver 5, and a select signal that is commonly given to the unit rows. Sl to SN and a clock signal CI-CM commonly given to the unit columns are supplied.

FIG. 6 explains this unit)-driver 5 in more detail, and shows the well-known NTSC system video signal processing circuit section 5.
1, a control circuit which receives the image data DA obtained by the video signal processing circuit 5, the horizontal synchronizing signal H1 and the synchronizing signal V, and generates the above-mentioned signals to be applied to the unit panel 4. 52.

The video signal processing circuit section 51 includes a tuner 51o1, an intermediate frequency amplification circuit 511, an audio detection amplification circuit 512, and a speaker 5.
13. This is a general circuit that includes a video intermediate detection circuit 514, a video circuit 515, a color circuit 516, a synchronous separation/divider circuit 517, vertical and horizontal oscillation circuits 518 and 519, etc.

Below, I will explain the configuration and operation of FIG. 6 using both FIGS. 7 and 8 together. First, the video signal processing circuit section 51
Then, the composite synchronizing signal obtained by the separation/frequency dividing circuit 517 is sent to the vertical oscillation circuit 518 and the horizontal oscillation circuit 519. A vertical auxiliary signal V and a horizontal synchronizing signal H are respectively generated. On the other hand, image data DA is obtained by the video circuit 515 and the color circuit 516.

Next, in the control circuit section 52, first, the image data
) A is set to the threshold f1M' by the threshold changing circuit 524.
is randomly modulated by the binarization circuit 525.
The image data D has a halftone converted as a 1^ signal of 2' or 0'l. Such binarization processing is called a teaser method. On the other hand, the timing circuit 52
Is it the same period pulse signal of vertical side synchronization signal V and horizontal synchronization signal H?
A vertical synchronizing pulse signal vP that is extracted and has a predetermined width.
The horizontal synchronizing pulse signal H'P is applied to a counter 72 and a decoder 73, and the vertical synchronizing pulse signal VP is applied to a counter 74, a decoder 75, and a blanking circuit 75, and the internal information of each circuit is reset to the base point. It works like T. The original clock signal CK from the oscillator 70 passes through the inverter 77 and the AND gate 71 to the counter 72 and M AND gates 80 when the blanking circuit 760 output BR is at the "0" level. Then, the count signal CT generated by the counter 72 every 9m clock counts is sent to the decoder 73, and the output of the decoder 73 and the clock signal CK are logically connected to the clock signal CJ by the AND gate 80. C2
, C3...CMs are sequentially output.

The frequency of the oscillator 700 is the sampling speed of all effective image data D included in 53 μs, which is approximately 84% of the effective scanning line length within the horizontal scanning period of 63.5 μs, and is, for example, the number of horizontal pixels m of the unit e panel. If M is 320, it will be approximately 6 MB2. Then the decoder 73
M number of scans from ? Each time the carry-over is completed, one carry-over number CY is output and sent to the carry-over number CY counter 74.

The counter 74 sends an output signal to the lever 75 every n counts of the carry signal CY, causes the decoder 75 to generate a select signal 8l-3N'i, and further outputs one output (number M) indicating the end of the select signal SN. The blanking signal BR is supplied to a blanking circuit 76 to generate a blanking signal BR.

This blanking signal BR is reset by the vertical synchronizing pulse signal VP in the blanking circuit 76 as described in 11J, and is held up to fl,6. The generation of the select signal is completely prohibited for a period of 22.5 hours of the horizontal synchronizing signal H remaining after one field is run.

On the other hand, an output signal synchronized with the clock signal CK is sent from the counter 72 to the luminance pA adjustment No. 1 generating circuit 78, and when one pulse m=16, the pulse width is varied between 1 and 15 clock cycles M width. A brightness adjustment signal BY is generated. Then, the brightness adjustment signal BY and the blanking signal BR are combined at the OR gate 79 to form the final brightness adjustment signal B.

In addition, the unit driver 5 includes a refresh circuit 526 and an enable control 527 as described above.
It also offers more versatility.

It should be noted that an automatic reset circuit may be used to set the reset signal 1° C. to n11 level for an appropriate period of time after the power is turned on, or a vertical synchronization signal may be used.

On the other hand, the enable signal may be generated by an external device if a switch is used to set the level to J) If'' or 01, or if a light ben input means is used.

Furthermore, it goes without saying that the AND gates, OR gates, etc. used in each circuit may be replaced by Nant gates, other gates, etc., as long as the functions can be obtained.

[Brief explanation of the drawing]

Figure 1 (b) is a diagram schematically showing the basic configuration of a unit display device and a display Φ unit formed by arranging it in a matrix, and Figures 2 and 3 are unit displays used in this invention. The basic configuration of the device is shown in Figure 4. Figure 4 is a time chart showing its operation. Figure 5 is a unit consisting of all M@N unit display devices.
FIG. 6 is a block diagram showing an embodiment of the present invention, and FIG. 7 is a diagram showing the operation of the horizontal synchronization signal and vertical synchronization signal of the TV signal. Figure 8 is an operation time chart showing the correspondence between valid image data included in the horizontal scanning period and clock pulses. 1... bow, ED array (light emitting element array), 2... module e-driver, 3... unit display device!
, 4...Unit stand panel, 5...e unit driver, 6...display unit (display device), 10...switching circuit, 15...shift register, 17.73.75... Decoater, 18°19...
・Current amplification circuit, 21, 22, 7x,, 74...
Counter, 70... Clock signal generation circuit (oscillator, /6... 2 pieces of blanging pulse generation circuit...
Brightness adjustment circuit, 79... Brightness signal synthesis circuit, D...
Image data, lζ...Reset signal, B...Brightness modulation signal, E...Enable signal, C, C1 to CM...
・Clock signal % S e S 1-8 N...Select signal, H...Horizontal synchronization signal, ■...Vertical same level 1 signal. Application Δ Agent Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] A display element array formed by connecting display elements with a specific number of pixels (m x n) in a matrix, a shift register that has the same number of stages as the number of pixels (m receives a select signal and image data from the shift register, when the select signal is at a first level, inputs the image data into the shift register from the first stage, and when the select signal is at a second level, outputs the final stage of the shift register from all the first stages. a switching circuit for inputting the m clock signals, a means for amplifying the total output current of the first m stages of the shift register and supplying it to the column lines of the mJ display cumulative array; means for sequentially selecting the row lines of the display element array;
A unit brightness panel is formed by connecting unit nice play devices in N rows and XM columns, including a brightness adjustment circuit that inhibits the selection operation of the row line based on a brightness adjustment signal, and this unit panel kmANu. and a unit-driver for displaying a television image, and the unit-driver binarizes valid image data within a horizontal synchronization period of the television image signal and commonly provides it to each unit display device of the unit panel. means and the vertical and horizontal KII signals of the television image signal are applied at the same time, and a predetermined operation is performed to primary output m clock signals to each column of the unit panel. clock signal generating means that returns the clock signal every time the horizontal direction signal is outputted by providing a pause period of a select signal generating means for sequentially outputting a select signal to each row of the unit panel at the timing of the inter-Kll signal; and a brightness adjustment signal common to each unit display device during the rest period of the clock signal.
means for generating a brightness adjustment signal to output, and means for stopping the clock signal output of the means of the unit panel according to the clock signal and the selection signal, and at the same time cobblestones a display blanking pulse to the output of the brightness adjustment signal generation means. A display device comprising: