JPS596103B2 - 4-phase PSK carrier wave regeneration circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention provides a four-phase PS (PhaseShlftKeyi
ng) Performing carrier wave recovery from the PSK signal in a demodulator that receives a signal and reproduces data from the signal 4
The present invention relates to a phase PSK carrier regeneration circuit.

The configuration of a conventional circuit of this type is shown in FIG.

In the figure, 1 is the input terminal for the received 4-phase PSK signal;
2 is a four-phase PSK carrier wave regeneration circuit, and 3 is an output terminal for the regenerated carrier wave. Next, the operation will be explained.

The received 4-phase PSK signal () is input to input terminal 1, and the 4-phase PSK carrier regeneration circuit 2 receives () this signal.
The carrier wave is recovered from the carrier wave s, and the recovered carrier wave s is outputted to the output terminal 3. This carrier wave regeneration is performed based on the following principle.

(to) the received signal is (to
It is expressed as (1).

Here, fo is the carrier frequency. This signal is passed through the multiplier (
When multiplied by 4 by (not shown), q()■[ni(o)]'' = e4j (2πfo +φ) = ej8πfo (2).

This is because 4φ=0m0d2π holds from equation (1).

Next, when this signal q() is input to a divider (not shown), its output becomes [q()]"=ej2πfo (3).

Therefore, the reproduced carrier wave s()■ cos2πfo(4 is obtained.

Further, when the divider is constituted by a digital circuit, the reproduced carrier wave s/(t) is as follows.

Since the conventional four-phase PSK carrier wave regeneration circuit is configured as described above, it has the disadvantage that the regenerated carrier wave is accompanied by a cycle skip phenomenon.

For example, if the divider malfunctions due to noise and a cycle skip occurs in the output, the recovered carrier wave s(t) will be as follows.

At this time, the modulation method is CPSK (C
If the modulation method is (OherentPhaseShiftKeying), data after this point will be erroneously demodulated. As described above, the conventional four-phase PSK carrier wave regeneration circuit has the disadvantage that cycle skips occur in the regenerated carrier wave. This invention was developed in order to eliminate the above-mentioned drawbacks of the conventional 4-phase P
It is an object of the present invention to provide a four-phase PSK carrier wave regeneration circuit that can output a normal recovered carrier wave even when a cycle skip occurs by adding a new cycle skip suppression circuit to the SK carrier wave regeneration circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the configuration of a 4-phase PSK carrier recovery circuit according to an embodiment of the present invention, where 2 is a conventional 4-phase PSK carrier recovery circuit, 4 is a newly added cycle skip suppression circuit,
5 is a reproduced carrier wave output terminal. FIG. 3 shows the configuration of the cycle skip suppression circuit 4, where 6 is a first delay circuit that delays the recovered carrier wave s(t) by a predetermined time τd, and 7 is the output of this π1st delay circuit 6. A first phase shifter that shifts the phase of the output d(t); 8 a second phase shifter that shifts the phase of the output d(t); 9 a recovered carrier wave r(t);
The phase difference θ between the phase shifter 7 and the output of the first phase shifter 7 is detected, and φ+(
t)-SgncOsO, the first phase detector 10 detects the phase difference θ5 between the recovered carrier wave s(t) and the output of the second phase shifter 8, and φ-(t)=SgncOs
a second phase detector which outputs a signal O'; 11 is the first phase detector;
A second delay circuit 12 delays the output φ (t) of the phase detector 9 by a predetermined time τr, and 12 detects the fall of the output of the second delay circuit 11 and delays the output φ (t) of the phase detector 9 by a predetermined time τr. a first pulse generator generating two consecutive pulses, 13;
1 is an exclusive OR gate having two inputs, the outputs φ+(t) and φ1(t) of the first and second phase detectors 9 and 10;
4 is a second pulse generator that detects the rising edge of the output e(t) of this exclusive OR gate 13 and generates one pulse; 15 is the output of this second pulse generator 14 and the A logical sum gate 16 calculates the logical sum of the outputs of the pulse generator 12 of 1;
), this shift register 16 consists of four registers, one registering "1" and the other three registers "0", and each time a pulse enters, the shift register 16 registers "1" and the other three registers "0".
are beginning to move cyclically.

In the above, the parts surrounded by the dashed line indicate four types of states that differ from the output of the first phase detector 9 and the output of the exclusive OR gate 13 depending on the amount of phase shift of the recovered carrier wave due to cycle skipping. Four control signals C1 to C that can take
A control signal generation circuit 30 that outputs 4 is configured. Also 1
7, 18, and 19 are phase shifters having phase shifts of 1, 1, and -i, respectively, and 20, 21, 22, and 23 are opened and closed under the control of the four outputs of the shift register 16, and the regenerated carrier wave These are switches that pass or block the outputs of the phase shifters 17, 18, and 19, respectively.
1 to C4 are "open", and when "0n", it is "closed". Further, the first delay circuit 6
It is assumed that the delay time τd satisfies the following relationship.

Here n is a positive integer. Next, the operation will be explained.

4 to 6 show time charts of signal waveforms of the circuit of FIG. 3 in the case of phase shift amounts +, π, and δ due to cycle skipping, respectively. First, consider a steady state with no cycle skips. At this time, the signal s(t) and the signal d(t
) is zero from equation (7), so φ+(t)=
((t)-1. At this time, if the outputs C, , C2, C3, and C4 of the shift register 16 are each 0001, (
Only the switch 20 is open and the output signal from the output terminal 5 is 1'.
Number 11 becomes →.

Next, consider the case where a cycle skip occurs at the time t=TO, as shown in FIG. 4, and the phase strength of the reproduced carrier wave s(t) changes.

The output d(t) of path 6 is in this case, 1st delay time becomes.

Therefore, the output φ+(t) of the first phase detector 9 is as follows.

Further, the output φ (t) of the second phase detector 10 is for all times t.

Therefore, at the time t=TO, the exclusive OR gate 13
The output e(t) changes from L'' to H'', and the second pulse generator 14 generates one pulse. This pulse causes the outputs Cl, C2, C3, and
C4 changes from 0001 to 1000, so that the open switch changes from switch 20 to switch 23.
Then, the recovered carrier wave s(t) is shifted by the phase shift amount −+δ phase shifter 1
9 and is output to the output terminal 5. As a result, from the time t=TO until the next pulse enters the shift register 16, the output carrier wave c(t) is the reproduced carrier wave s(t) whose phase is shifted by one due to the cycle skip. 3π et al., that is, the reproduced carrier wave s(t) is phase-shifted by 1π.

On the other hand, the output φ+(t) of the first phase detector 19 is t=TO
At the point in time, the signal changes from "1" to "-1", is delayed by a predetermined time τr in the second delay circuit 11, and is input to the first pulse generator 12.

This first pulse generator 12 has t=TO+τr and t
The two pulses of = are output as the output p(t) of the OR gate 15 and input to the shift register 16. By the first pulse of the above two pulses, the outputs Cl, C2, C3, C3 of the shift register 16 become t=TO+τ
At time r, the switch changes from 1000 to 0100, and at the same time the switch in the open state moves from switch 23 to switch 22, and the recovered carrier wave s(t) is transferred to phase shifter 18 with a phase shift amount of 1π.
The signal is output to the output terminal 5 through the . As a result, the output carrier wave c
From t=TO+τr until the next pulse enters the shift register 16, the phase of the recovered carrier wave s(t), which has been phase-shifted by cycle skipping, is further increased by 1π.
That is, the phase of the reproduced carrier wave s(t) is shifted by -7.

Next, the second of the two panores by the first pulse generator 12 (from this, the outputs Cl, C2, C3, C4 of the shift register 16 are t=TO+τr+
At the time of τs, the switch changes from 0100 to 0010, and at the same time the switch in the open state changes from switch 22 to switch 21.
The recovered carrier wave s(t) is transferred to phase shifter 1 with a phase shift amount of 1.
7 and is output to the output terminal 5.

As a result, the output carrier wave c(t) is a phase shift of s(t), which has just been phase-shifted by the cycle skip, by an additional factor, and is equal to the phase of s(t) before the cycle skip occurs. Become. In this way, after the time t=TO+τr+τs, cycle skips are suppressed and the correct carrier wave is regenerated. Also, as shown in Figure 5, t=TO
A cycle skip occurs at the point in time, and the recovered carrier wave s(t)
When the phase of d(t) changes by π, the output d(t) of the first delay circuit 6 becomes d(t).

Therefore, the output φ+(t) of the first phase detector 9 is as follows.

Further, the output φ-(t) of the second phase detector 10 is as follows.

Therefore, in this case, the output e(t) of the exclusive OR gate 3 remains unchanged at 0'', and the second pulse generator 14 does not generate a pulse. Output φ
+(t) changes from ``1'' to ``-1'' at the time of t=TO, so the first pulse generator 12 outputs t=TO+τr.
A pulse is generated at each time point of t-TO+τr+τs. Outputs Cl, C2, C3, and C4 of the shift register 16 become 000 due to the first pulse of these two pulses.
1 to 1.000, the switch 23 is opened instead of the switch 20, and the reproduced carrier wave s(t) is outputted to the output terminal 5 through the phase shifter 19 with a fixed phase shift amount. As a result, the phase of the output carrier wave c(t) is s(t
) is phase shifted by one degree. Next, by the second pulse of the two pulses, the outputs Cl, C2, C3, and C4 of the shift register 16 change from 1000 to 0100 at t=TO+τr+τs, and the switch 22 opens. The reproduced carrier wave s(t) is outputted through the phase shifter 18 with a phase shift amount of 1π. As a result, the phase of the output carrier c(t) is equal to the phase shift of s(t) before the cycle skip occurs after the time t==TO+τr+τs, and in this way the cycle skip is suppressed. Ru. Further, as shown in FIG. 6, if a cycle skip occurs at the time t:TO and only the phase force of the recovered carrier wave s(t) changes, the output d of the first delay circuit 6 (t)
Hato becomes.

Therefore, the output φ+(t) of the first phase detector 9 is for all t.

Further, the output φ-(t) of the second phase detector 10 is as follows.

Therefore, in this case, the output c(t) of the exclusive OR gate 13
The second pulse generator 14 generates one pulse. Due to this pulse, the outputs Cl, C2, C3, and C4 of the shift register 16 change from 0001 to 1000, the switch 23 opens instead of the switch 20, and the reproduced carrier wave s(t) changes from the phase shift amount to the phase shifter. 19 and is output. As a result, the output carrier wave c(t)
After the time t2TO, the phase of s(t) becomes equal to the phase of s(t) before the cycle skip occurs, and in this way the cycle skip is suppressed. By the way, in the above explanation, the outputs Cl, C2, C3, C4 of the shift register 16
It is assumed that the initial states of are all 0001, but it is not an essential problem whether this initial state is 0001, 1000, 0100, or 0010.

This is because the reproduction π for the carrier wave of the received signal r(t)
? This is because the carrier wave s(t) originally has four states of phase uncertainty: 0, 7, π, and I, and the above problem is absorbed by this phase uncertainty.

In the above embodiment, the phase shift amount of the phase shifters 17 to 19, π,
? These phase shifters were connected in front of each switch 21, 22, and 23, but this meant that three phase shifters with the current phase shift amount were connected in series, and the output of each stage was connected to each switch 21. ,22,
Of course, it may be connected to 23. Further, in the above embodiment, the control signal generation circuit 30 is connected to the first phase detector 9
The output of the first phase detector 9 generates two pulses, and the output of the exclusive OR gate 13 generates one pulse. Two pulses may be generated by the output of the OR gate 13.

Further, the output of the second phase detector 10 may be used instead of the output of the first phase detector 9, and the second delay circuit 11 may be inserted on the exclusive OR gate 13 side. In either case, by changing the connections between the outputs C1 to C4 of the shift register 16 and the switches 20 to 23, the same function as in the above embodiment can be achieved. Furthermore, when the reproduced carrier wave s(t) is given as a digital waveform like force (5), an AND gate is used in place of the switches 21 to 23, and these outputs are passed through an OR gate to the output terminal c( t).

Further, the present invention is not limited to the 4-phase PSK carrier wave regeneration circuit, but may be applied to signal processing in which cycle skipping in the above sense is a problem, and has the same effect as the above embodiment ε.

As described above, according to the present invention, since the cycle skip suppression circuit is added to the four-phase PSK carrier wave recovery circuit, cycle skips can be suppressed, and a recovered carrier wave with good characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a conventional 4-phase PSK carrier wave recovery circuit, FIG. 2 is a block circuit diagram of a 4-phase PSK carrier wave recovery circuit according to an embodiment of the present invention, and FIG. Block circuit diagram of the block suppression circuit, Figure 4 a-g
5A to 5G are operational waveform diagrams of each part of the circuit in FIG. 3 when the phase shift amount of the reproduced carrier wave due to cycle skipping is π, and FIGS. g is an operating waveform diagram of the circuit of FIG. 3 when the above phase shift amount is large. 2... 4-phase PSK carrier wave regeneration circuit, 4...
... Cycle skip suppression circuit, 6 ... Delay circuit, 7 ... First phase shifter, 8 ... Second
phase shifter, 9...first phase detector, 10...
. . . Second phase detector, 13 . . . Exclusive OR gate, 17-19 . . . Phase shifter 20-23
...Switch, 30...Control signal generation circuit.

Claims (1)

[Claims] 1. In a 4-phase PSK carrier wave regeneration circuit that regenerates a carrier wave from a received 4-phase PSK signal, there is a delay circuit that delays the regenerated carrier wave for a predetermined time, and a phase shift of -π/4 or π/4 for the output of this delay circuit, respectively. first and second phase shifters that detect the phase difference between each output of the first and second phase shifters and the recovered carrier wave; 1. An exclusive OR gate with the output of the second phase detector as two inputs, and a recovered carrier wave by cycle skipping from the output of the first or second phase detector and the output of the exclusive OR gate. varies depending on the amount of phase shift of 4
A control signal generation circuit outputs four control signals that can take different states, and the regenerated carrier wave is π/2, π,
The regeneration device includes three phase shifters that shift the phase by 3π/2, and four switches each having inputs of the regeneration carrier wave and the outputs of the three phase shifters and respectively being opened and closed by the four control signals. A four-phase PSK carrier wave regeneration circuit comprising a cycle skip suppression circuit that suppresses cycle skips of a carrier wave.