JPS5961163A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5961163A JPS5961163A JP57171244A JP17124482A JPS5961163A JP S5961163 A JPS5961163 A JP S5961163A JP 57171244 A JP57171244 A JP 57171244A JP 17124482 A JP17124482 A JP 17124482A JP S5961163 A JPS5961163 A JP S5961163A
- Authority
- JP
- Japan
- Prior art keywords
- resistance value
- resistor
- polycrystalline silicon
- resistance
- polysilicon resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置の製造方法、詳しくは半導体装置の
多結晶シリコン（ポリシリごＩン）の抵抗値をモニター
しながら前記ポリシリコン抵抗にイオン注入をなしその
抵抗値を高精度に変更させる方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device. This invention relates to a method of implanting and changing its resistance value with high precision.
（２）技術の背景
半導体装置のポリシリコン抵抗にイオン注入をなし当該
抵抗の抵抗値を低下させることが行われている。(2) Background of the Technology Ions are implanted into polysilicon resistors of semiconductor devices to lower the resistance value of the resistors.
第１図には半導体装置のポリシリコン抵抗が１ｌｌｉ面
図で示され、同図において、■は酸化膜（二酸化シリコ
ン膜）、２はポリシリコン抵抗、３は絶縁膜（例えぼり
ん・シリケート・ガラス（ＰＳＧ）膜）、４はアルミニ
ウム配線、５は保護膜（ＰＳＧ膜）をそれぞれ示し、ア
ルミニウム配線４は絶縁膜３を成長した後にそれに窓開
げをなし、しかる後にアルミニウムを蒸着することによ
って形成され、ポリシリコン抵抗２と接続されている。In Figure 1, a polysilicon resistor of a semiconductor device is shown in a 1lli plane view. 4 is an aluminum wiring (glass (PSG) film), 5 is a protective film (PSG film), and the aluminum wiring 4 is formed by growing an insulating film 3, forming a window thereon, and then depositing aluminum. is formed and connected to polysilicon resistor 2.
ポリシリコン抵抗２の導電型が図示の如くｎ＋ρｎ＋で
あったとすると、この抵抗は第２図の等価回路図に示さ
れる如くタイオートが逆に接続されたものと同様の構成
となり、とちら方向に電圧をかけても電流は流れない、
すなわち、どちら方向にバイアスをかけてもいずれかの
ダイオードには逆バイアスがか＆Ｊられるので電流が流
れない。すなわちポリシリコン抵抗２は高抵抗の状態に
ある。Assuming that the conductivity type of the polysilicon resistor 2 is n+ρn+ as shown in the figure, this resistor has a configuration similar to that of a tie-out connected in reverse as shown in the equivalent circuit diagram of FIG. No current flows even if voltage is applied
That is, no matter which direction bias is applied, current will not flow through either diode because it is reverse biased. That is, polysilicon resistor 2 is in a high resistance state.
ここで、ポリシリコン抵抗２のｐ形部分にｎ形不純物を
イオン注入すると、ポリシリコン抵抗２の導電型はｎ”
ｎ ｎ＋となって電流が流れる、すなわらポリソリコ
ン抵抗２は低抵抗の状態になる。上記の如くに形成した
集積回路はポリシリコン抵抗の導電型を変えること、ず
なわら抵抗値を変えることによってプログラムを作成を
可能にする。Here, when an n-type impurity is ion-implanted into the p-type part of the polysilicon resistor 2, the conductivity type of the polysilicon resistor 2 becomes n''
n n+ and a current flows, that is, the polysilicon resistor 2 becomes in a low resistance state. The integrated circuit formed as described above can be programmed by changing the conductivity type of the polysilicon resistor and by changing the resistance value.
（３）従来技術と問題点
従来のイオンの作り方には放電によるイオン化と加熱に
よるイオン化とがあったが、いずれの方法によってもイ
オンビームのスポットの直（そを１．０μｍ以Ｆにはす
ることができず、集ｆｆ１ＩＬｉｌ路のｉＲ’に細化の
傾向に対応することができなくなりつつある。(3) Conventional technology and problems Conventional techniques for producing ions include ionization by electric discharge and ionization by heating, but both methods are effective at directing the ion beam spot (to a diameter of 1.0 μm or more). Therefore, it is becoming impossible to cope with the trend of thinning of iR' of the collection ff1ILil path.
また、従来の方法では、イオン注入を終ってのなりれば
抵抗値の変更があったか否かが判らず、・イオン注入を
なしつつ抵抗値を１Ｊｌｌｌ定して商Ｉｉ’ｉ度に特定
の抵抗値にまで抵抗値を調整する（１リミンク）ごとは
未だなされζいない。In addition, in the conventional method, it is difficult to tell whether the resistance value has changed after ion implantation. Adjustment of the resistance value to the desired value (1 remink) has not yet been carried out.
（４）発明の目的
本発明は上記従来の問題点に鑑の、ビーム・スポットを
小に絞ったイオンビームを半導体装置の配線に接続され
た多結晶シリコン抵抗にイオン注入し、該抵抗の抵抗値
をモニターしつつ変更させ、集積回路が形成された後に
抵抗値を変えてプログラムを作成することを可能にする
半導体装置の製造方法を提供することを目的とする。(4) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention aims to implant ions into a polycrystalline silicon resistor connected to the wiring of a semiconductor device using an ion beam with a narrowed beam spot. It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows a program to be created by changing the resistance value while monitoring the resistance value after an integrated circuit is formed.
（５）発明の構成
そしてこの目的は本発明によれば、酸化膜の上に形成さ
れ半導体装置の配線に接続された多結晶シリコン抵抗の
抵抗値をモニターしつつ前記多結晶シリコン抵抗にイオ
ン注入し、該抵抗の抵抗値を変更することを特徴とする
半導体装置の製造方法を提供することによって達成され
る。(5) Structure and object of the invention According to the present invention, ions are implanted into the polycrystalline silicon resistor while monitoring the resistance value of the polycrystalline silicon resistor formed on the oxide film and connected to the wiring of the semiconductor device. However, this is achieved by providing a method for manufacturing a semiconductor device characterized by changing the resistance value of the resistor.
（６）発明の実施例
本発明の方法の実施においては、フィールド・−エミッ
ション型イメン・ソース（Ｆｉｅｌｄ Ｅｍｉｓ−ｓｉ
ｏｎ Ｉｏｎ ５ｏｕｒｃｅ ）を用いる。かがるイオ
ン・ソースを用いることにより、イオンのビーム・スポ
ットを１．０μ粕以下０．１．ｕｍ程度にまで絞ること
が可能であり、集積回路の微細化に十分対応することが
可能となる。また、ビームに重圧を印加することによっ
て任意の位置にビーム・スポットを微調整でもって動か
すことが可能になる。(6) Embodiments of the Invention In carrying out the method of the present invention, a field-emission type source (Field Emis-si) is used.
on Ion 5source). By using a bending ion source, the ion beam spot can be reduced to 0.1 μm or less by 1.0 μm. It is possible to narrow it down to about um, and it becomes possible to sufficiently cope with the miniaturization of integrated circuits. Furthermore, by applying heavy pressure to the beam, it becomes possible to move the beam spot to any desired position with fine adjustment.
かかるイオン・ソースを用い、第１図に矢印で示す如く
保護膜５の上からポリシリコン抵抗２のｐ形部分にトナ
ー不純物をイオン注入し、ｐ形部分をｎ形部分に変える
と、ポリシリコン抵抗２の導電型はｎ”ｎｎ＋となり、
電流が流れる、ずなわら抵抗値は高抵抗から低抵抗の状
態になる。Using such an ion source, toner impurities are ion-implanted into the p-type part of the polysilicon resistor 2 from above the protective film 5 as shown by the arrow in FIG. 1, and the p-type part is changed into an n-type part. The conductivity type of resistor 2 is n”nn+,
When current flows, the resistance changes from high resistance to low resistance.
かくして一般に、ポリシリコン抵抗２の導電型がｎ”ｐ
ｎ ＋ 、 ｎ”ｎｎ ＋ 、 ｎ ＋
ｉｎ” （）こ だ し 、ｉはｐ形でもｎ
形でもないイントリンシックの状態）のものを、ｎ１ｎ
ｎ＋、ｎ＋ｎ′ｎ４、ｎ”ｎｎ’の導電型に変更するこ
と、ずなわら抵抗値が高い状態から低い状態に変え、電
流が流れるように変更し、プログラムを作成することが
可能になる。Thus, in general, the conductivity type of the polysilicon resistor 2 is n''p.
n + , n”nn + , n +
in” (), i can be p-type or n
n1n
It becomes possible to create a program by changing the conductivity type to n+, n+n'n4, n''nn', changing the resistance value from a high state to a low state, and changing the state so that a current flows.
」二記したイオン注入は、フィールド・エミッション型
イオン・ソースを用い、ポリシリコン抵抗２の微細部分
に注入することが可能で、集積回路が完成した後に抵抗
値を変えてプログラムを作成することができる。かくし
て、本発明の方法は、ランダム・アクセス・メモリ （
ＲＡＭ）に冗長性を４１与するために実施され、また読
出し専用メモリ（ＲＯＭ ）にも応用可能である。The ion implantation described in Section 2 can be performed using a field emission type ion source and can be implanted into minute parts of the polysilicon resistor 2, and it is possible to create a program by changing the resistance value after the integrated circuit is completed. can. Thus, the method of the present invention can be applied to random access memory (
It is implemented to provide redundancy in RAM) and is also applicable to read-only memory (ROM).
更に本発明の方法においては、ウェハを５００℃程度に
加熱しておいて、チップの端のモニター抵抗を第１図の
ポリシリコン抵抗２と同様に構成し、それの抵抗値を測
定しながらイオン注入を行い、そのウェハの最適ドース
を決めることが可能となる。または、上記の方法におい
て抵抗値を測定しなからウェハを５００℃に加熱し、か
つ、イオン注入を行ってもよい６５００°Ｃの加熱はイ
オン注入の活性化のためなされるものであるが、アルミ
ニウム配線とかＰＳＧ膜の反応を惹起することのない−
よう設定した。Furthermore, in the method of the present invention, the wafer is heated to about 500°C, a monitor resistor at the edge of the chip is constructed in the same manner as the polysilicon resistor 2 in FIG. It becomes possible to perform an implant and determine the optimum dose for the wafer. Alternatively, in the above method, the wafer may be heated to 500° C. without measuring the resistance value, and ion implantation may be performed.Heating to 6500° C. is performed to activate the ion implantation. Does not cause reactions with aluminum wiring or PSG film.
I set it like this.
以上に説明した如くに、本発明の方法においては、ポリ
シリコン抵抗の抵抗値を測定しつつその導電型をｐ形か
らｎ形へ、またはｎ形からｐ形へ変えること、すなわち
高抵抗を低抵抗に、また低抵抗を高低抗に変更すること
が可能になるだけでなく、ある特定の抵抗値に、高精度
に調整（トリミング）が可能となり、ポリシリコン抵抗
２を精度よ（特定の抵抗値に変えることができる。As explained above, in the method of the present invention, the conductivity type is changed from p-type to n-type or from n-type to p-type while measuring the resistance value of a polysilicon resistor. Not only is it possible to change the resistance value from low resistance to high or low resistance, but also it is possible to adjust (trimming) the polysilicon resistor 2 to a specific resistance value with high precision (trimming the resistance value to a specific resistance value). can be changed to a value.
（７）発明の効果
以上、詳細に説明した如く、本発明の方法によれば、で
き上がった集積回路の微細部分にイオン注入が可能とな
り、また、ポリシリコン抵抗の抵抗値をモニターしなが
らイオン注入をなすことによってポリシリコン抵抗の抵
抗値を微調整で変更することができる効果がある。(7) Effects of the Invention As explained in detail above, according to the method of the present invention, ions can be implanted into minute parts of a completed integrated circuit, and ions can be implanted while monitoring the resistance value of a polysilicon resistor. By doing so, there is an effect that the resistance value of the polysilicon resistor can be changed by fine adjustment.
第１図はポリシリコン抵抗をもった半導体装置要部の断
面図、第２図は第１図の配線の等価回路図である。
１−酸化膜、２−ポリシリコン抵抗、
３−絶縁膜（ＰＳＧ膜）、４−アルミニウム配線、５−
保護膜（ＰＳＧ膜）FIG. 1 is a sectional view of a main part of a semiconductor device having a polysilicon resistor, and FIG. 2 is an equivalent circuit diagram of the wiring shown in FIG. 1-Oxide film, 2-Polysilicon resistor, 3-Insulating film (PSG film), 4-Aluminum wiring, 5-
Protective film (PSG film)
Claims (1)
結晶シリコン抵抗の抵抗値をモニターしつつ前記多結晶
シリコン抵抗にイオン注入し、該抵抗の抵抗値を変更す
ることを特徴とする半導体装置の製造方法。A semiconductor characterized in that, while monitoring the resistance value of a polycrystalline silicon resistor formed on an oxide film and connected to wiring of a semiconductor device, ions are implanted into the polycrystalline silicon resistor to change the resistance value of the resistor. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171244A JPS5961163A (en) | 1982-09-30 | 1982-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171244A JPS5961163A (en) | 1982-09-30 | 1982-09-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5961163A true JPS5961163A (en) | 1984-04-07 |
Family
ID=15919711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57171244A Pending JPS5961163A (en) | 1982-09-30 | 1982-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961163A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61160961A (en) * | 1985-01-08 | 1986-07-21 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63114159A (en) * | 1986-08-08 | 1988-05-19 | シリコニクス インコ−ポレイテツド | Trimmable high value polycrystalline silicon resistor |
-
1982
- 1982-09-30 JP JP57171244A patent/JPS5961163A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61160961A (en) * | 1985-01-08 | 1986-07-21 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63114159A (en) * | 1986-08-08 | 1988-05-19 | シリコニクス インコ−ポレイテツド | Trimmable high value polycrystalline silicon resistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2697812B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| JP3032138B2 (en) | Method for manufacturing high-density MOS power device and high-density MOS power device manufactured by the method | |
| US4617723A (en) | Method and device for creating an activatable conducting link in a semiconductor device | |
| JPS62500623A (en) | Method of resistor trimming by metal transfer | |
| KR940001890B1 (en) | Polysilicon resistor manufacturing method and semiconductor device | |
| US10181440B2 (en) | Semiconductor device | |
| JPS5880852A (en) | Manufacture of semiconductor device | |
| JP2775503B2 (en) | Manufacturing method of junction gate type field effect transistor | |
| TW200306647A (en) | Method for fabricating transistor | |
| JPH04373147A (en) | Fuse structure of semiconductor device | |
| JPS6358371B2 (en) | ||
| JPH0467336B2 (en) | ||
| CA1245370A (en) | Temperature stable self-protected thyristor and method of producing | |
| JPS5834943A (en) | Semiconductor device and manufacture thereof | |
| JP3175280B2 (en) | Ion implantation method | |
| JPS6068617A (en) | Ion milling method for semiconductor device | |
| JPS62154622A (en) | Manufacture of semiconductor device | |
| JPH0642493B2 (en) | Method for manufacturing semiconductor device | |
| JP3095150B2 (en) | Semiconductor device | |
| JPS6084836A (en) | Semiconductor device | |
| JPS6020890B2 (en) | semiconductor equipment | |
| JPS60245251A (en) | Semiconductor device | |
| KR980012554A (en) | Method for manufacturing a high resistance semiconductor device | |
| JPH08222702A (en) | How to adjust the threshold voltage of a transistor | |
| JPS5837965A (en) | Manufacture of semiconductor device |