JPS5961874A - Character magnification circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character enlargement circuit that displays characters enlarged vertically by N times using a character dot bargain signal read from a character pattern memory.

In recent years, with the rapid development of electronic technology, character displays have been used in e-type devices. When displaying this character, C1 reads out the character pattern memory in which character dot display signals to be displayed by dots of various characters p, π-, knXm are stored, and the characters read from this character pattern memory are displayed. A target character is displayed by a combination of dots using a dot display signal. In this case, the size of the displayed characters is within the specified size specified in advance by nXm dots.

However, when displaying characters in a part that you want to emphasize, such as a heading part, there may be cases where you want to enlarge the character size in the vertical direction compared to other parts, but in the above configuration, such enlarged display I couldn't do it all.

To solve this problem, the character dots read out from the character pattern memory are supplied to all the central processing units, and converted into enlarged character dot display signals through software processing. There are some that display enlarged characters.

However, in such enlarged display of characters, since the enlargement processing is performed by software processing, the processing time increases and the enlarged characters cannot be displayed quickly. In addition, when enlarging characters by software processing,
This has problems such as a complicated and expensive configuration.

Therefore, an object of the present invention is to provide a character enlarging circuit that can quickly display characters enlarged in the %I:fL force direction, although the circuit has a Dutch construction.

In order to achieve such an object, the present invention makes the readout period of the character pattern memory tN times the period at which the readout signal of the character pattern memory is taken in for display. For display purposes, the displayed characters are displayed by multiplying them by N in the vertical direction by adding υ eight times each. Hereinafter, a character enlargement circuit according to the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a character enlarging circuit according to the present invention. In the figure, l is a central processing unit, and ports 'nP1. to which address signals AB are connected.
INTERABLED BOAT INT.

The read signal ratio] is connected to the port group P3 to which the baud Pz and data bus DB are connected. 2
3 is a first decoder which decodes the address signal Ash supplied to C via the address signal AB and generates control signals a and b'j; is a latch circuit in which the output signal C becomes @L" by being read by the control signal υ, and 4 is an N frequency divider circuit that divides the frequency of the read clock signal φkN. In this case, is a frequency divider circuit using a binary counter. Reference numeral 5 denotes a selector that selects and outputs the read clock signal φ supplied to the input port A and the read clock signal φ' supplied from the input port A) BKN frequency divider circuit 4;
When the output signal C supplied from the latch circuit 3 to the select port SL becomes H'', the read clock signal φ' supplied to the input port B is selected and output. 6 is a character pattern memory in which the dots of each character represented by a 12 x 8 dot matrix is stored as a character P indication signal, which is connected from the central processing unit l to the address bus. Address signal A supplied via ABi
The character pattern to be read is specified by SK. Then, when the read clock signal φ or φ' is supplied from the selector 5, the character dot signal DS of the character pattern represented by the dot matrix is set in all units of -9 rows in synchronization with this read clock signal. It is sequentially output as an 8-bit parallel signal. 7 is an address signal AS supplied via address node ABg.
A second decoder generates an address enable signal T, which specifies the character pattern memory 6 and a register 9 to be described later, by decoding it. In/noter for supplying all enable signals AEI, 9
is a register which receives as input the fc-character dot display signal DS read from the character pattern memory 6, and its output end is connected to the data bus DB. IO is an OR gate that receives the address enable signal AE and the read signal RD i, and its output enables the register 9.

In the character enlarging circuit configured in this manner, when the central processing unit l outputs an address signal As corresponding to the character to be displayed to the address signal AB as shown in FIG. 2(a). , the second decoder 7 receives this address signal AS
By decoding the υ address enable signal T is generated, and after being inverted in the inverter 8, the signal shown in FIG. 2 (
The address I shown in b) is also the enable signal AP, which enables the character pattern memory 6. When the character pattern memory 6 is supplied with the address enable signal AEI, a data valid signal DVi is generated as shown in FIG. Loved port feeds mind punishment. The central processing unit 1 is in an interlaced mode for displaying the entire contents read from the character pattern memory 6 by the data read signal DV.

Here, the latch circuit 3 is normally in the reset mode, and its output signal C is LH. and,
The selector 5 inputting the output signal cf selects the read clock signal φ shown in FIG. 2(d) supplied to the input port and supplies it to the character pattern memory 6.

As a result, each time the read clock signal φ is supplied to the character number turn memory 6, an 8-bit parallel signal is generated in units of rows and columns of a character pattern represented by 12×8 dots as shown in FIG. 2(e). Similarly, the character dot display signals DS are sequentially read out. Tsuma υ,
Since the vertical direction is composed of 12 dots, reading out the character dot display signal DS for one character is completed by reading out the signal in units of 8 bits 12 times.

Here, the central processing unit 1 generates an address enable signal AT from the second decoder 7 by sending an address signal AS specifying the register 9. In addition, since the central processing unit 1 generates a read signal RD t- from the output port P in synchronization with the read clock signal φ, the output signal of the OR game) 10 synchronizes with the read signal n. Therefore, the character dot display signal DS read out from the character pattern memory 6 in units of 8 pits is enabled in the register 9.
At this time, the data are sequentially transmitted in accordance with the processing timing of the central processing unit l. Then, this 8-bit character dot signal DS is transmitted from registers 9 to 12.
When the forwarding message is sent out, characters in the 2×8 dot configuration shown in FIG. 3 are displayed.

Next, when an instruction is given to enlarge the display in the vertical direction, the central processing unit 1 generates an address signal As indicating the enlargement mode, and the output signal a of the first decoder 2 goes high. '', the latch circuit 3 is set, so its output signal C continues to be held at ``H'', and the selector 5, which uses this output signal cf select input, receives the input signal and supplies it to the input port B. The readout clock signal φ' is switched to the readout clock signal φ' and supplied to the character and e-turn memory 6. In this case, the readout clock signal φ' is the one whose frequency is divided by two in the readout clock signal φkNO frequency circuit 4. Therefore, the cycle is doubled as shown in FIG. 2(f), and accordingly, the generation cycle of the character dot display signal DS' output from the character nolin memory 6 is also doubled. On the other hand, since the central processing unit l generates the read signal RDt- in synchronization with the read clock signal φ, the register 9 outputs the read signal RDt- within the generation period of the character dot expense signal DS'. Since it is not enabled twice, the character dot display signal DS' with the same content is sent twice. B' is sent 24 times to make up one character, and when this character dot display signal DS"i is received and displayed, a character enlarged twice in the vertical direction is displayed as shown in Figure 4. Ru.

Next, when returning from displaying enlarged characters to displaying normal characters, the central processing unit l generates an address signal As indicating the normal mode, and the output signal b'(r
Seratos goes to ``H''.

When this output signal reaches tHs, the latch circuit 3 is reset and its output signal C becomes "L", and the selector 5 selects the read clock signal φ supplied to the input port. By supplying the character pattern memory 6, the normal mode is returned.

In the above-mentioned embodiment, a case has been described in which enlarged characters doubled in the vertical direction are displayed, but it can be set arbitrarily by increasing the division ratio of the N frequency divider circuit 4. In other words, in the enlargement mode, by setting the cycle of the read clock signal supplied to the character pattern memory to be N times the print cycle of the read character dot display signal, The characters enlarged by N times will be displayed.

As explained above, according to the character enlargement circuit according to the present invention, displayed characters can be enlarged in the vertical direction by hardware processing without performing software processing as in the past, so the configuration is simplified. In addition, it has various excellent effects such as speeding up the processing for enlargement.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a character enlargement circuit according to the present invention, #I2 (a) to (g) are operational waveform diagrams of each part of the circuit shown in FIG. 1, and FIGS. 3 and 4 are Standard characters and double horizontally enlarged characters? FIG. l...Central processing unit, 2.7...1st. 2nd decoder, 3... latch circuit, 4... N frequency divider circuit, 5
...Selector, 6...Character pattern memory, 8...
- Innovator, 9...Register, 10...Or gate. Applicant: Nippon Electric Co., Ltd. Figure 3 Figure 4

Claims (1)

[Claims] (1) In normal mode, the read clock signal is selected and output, and in enlargement mode, the read clock signal (i-
A selector selects and outputs the output signal of the frequency dividing circuit that divides the frequency by N, and each dot of various character patterns represented by a dot matrix is stored as a character dot display signal, and the clock signal supplied from the selector is A character pattern memory that synchronously outputs a character dot display signal as a parallel signal for each horizontal row of the dot matrix, and a read signal that takes the output signal of this character pattern memory as input and synchronizes with the read clock signal every time it is supplied. In the expansion mode, the character dot display signal with the same content is outputted from the register iN times each by multiplying the reading period of the character dot memory by N times. A character enlargement circuit characterized by displaying enlarged characters 'fr' multiplied by N in the direction.