JPS5961886A - Drive circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a conductor array in an AC (alternating current) plasma display device.

[Background technology]

In conventional AC plasma display devices, arrays of parallel conductors are arranged orthogonally facing each other on the inner surface of a gas-filled panel, with the intersections of the conductors forming gas cells. A discharge voltage can be applied to selectively ionize the gas cells to produce a visual display of specific shapes or information. During discharge, the cell generates a high charge FE which is combined with a low level hold signal.

The plasma display device is equipped with a circuit that generates a holding chamber E' consisting of a periodic voltage that maintains the discharge of the gas cell at a frequency sufficient to sustain the discharge. This preserves the form and information of the patent in its current form as a visual representation.

The protection voltage is also used to control all write and erase operations. The peak of the protection voltage is about 200μ.

The generation of this Shimada hold signal is controlled by a low voltage circuit that is responsive to digital logic signals from an external processor or controller, which logic signals depend on the operations being caused to occur in the plasma device. Since the voltage levels of the holding signal and the logic signal are different, a device for communication between them is required to fully operate the plasma apparatus. For example, U.S. Pat.
No. 73256, No. 4097856, etc. use pulse pulses to transmit and receive signals while maintaining insulation between low voltage and high voltage circuits.
It uses a transformer. It is desired to replace this pulse transformer with a low-cost semiconductor circuit.

One problem in plasma devices is controlling the displacement time of switching waveforms such as holding voltages. Although techniques already exist to control displacement time at low rates of change, this becomes rapidly difficult as rates of change and voltages increase. This becomes particularly difficult when high power vertical field effect transistors (VFETs) are used in the drive circuit of the plasma device.

High power VFETs exhibit wide bandwidth characteristics and tend to oscillate unless their gate drive circuits have higher frequency characteristics. Requires the use of circuits. There are also differences in gain between devices, and each device requires different gate-to-source inputs in order to obtain the same output change rate.

Conventional plasma device drive circuits have not paid much attention to the change time, ie, the control of the rise and fall of the switch waveform, such as the holding voltage. I was only thinking about speeding up the displacement time. In large plasma devices, fast displacement times cause large currents within the device. It is desirable to control the displacement time of the switch waveform to a fixed time or a fixed rate of change.

An object of the present invention is to use a low-cost semiconductor circuit to control the displacement time of a switch waveform to a fixed time or -indication rate, and to isolate a high-voltage pulse circuit from a low-voltage control circuit without using a transformer. An object of the present invention is to provide an improved plasma display device drive circuit that communicates digital signals across its floating boundaries to a low voltage control circuit.

[Summary of the invention]

The present invention provides a plasma device drive circuit in which the displacement of the holding voltage waveform is controlled to be constant over a certain period of time. The displacement time is defined as a constant time independent of electrical changes that vary during operation of the circuit.

A VFET is used as an output switch to create a holding voltage to the gas cell. Some sources of VFET are VF
When ET is not used, it floats up and down.
The gates are connected to the sources of the VFETs when they are not in use. The low voltage circuitry used to drive the vFBT also floats with the source potential.

Lower-cost semiconductor circuits have replaced the transformers traditionally used to route digital logic signals from external controllers and processors to floating, low-voltage drive circuits. This scheme allows logic signals to be sent across the boundary of the high voltage section to the low voltage drive circuit without a transformer.

The song format of the present invention is such that the displacement time of the holding voltage waveform is controlled to a constant rate of change.

[Explanation of Examples]

In FIG. 1, a drive circuit 20 of the present invention has a switch circuit 12 for receiving digital logic signals (mainly T'l'L level) from an external controller 11 or a processor (concave). These logic circuits are used only to control the holding operation of the plasma device. It does not provide information to be displayed on a plasma device.

The switch circuit 12 receives the logic signal and sends the information to the control circuit 13. It is the control circuit 13 that determines the displacement time of the holding waveform applied from the VFET 14 to the cell 16.

The control circuit 13 includes a low voltage gate drive circuit that drives the gate of the VFET 14, a current source, and a gate isolation circuit that isolates the low voltage gate drive circuit from the high voltage source 15. These functions will be explained in detail later with reference to FIGS. 6-7.

1 of the holding waveform sent from VFET output 14 to cell 16
An example can be seen in Figure 2. As shown in US Pat. No. 4,263,534, it is difficult to obtain a 200V VFET with characteristics that can be used in plasma panels. Therefore, in order to obtain a waveform k'fl of 200V from peak to peak, the entire circuit must be designed in two stages with 100V VFETs in each stage. The first stage has the waveform shown in FIG. 2 and moves from point 17 to point 18 with a width of 100 from peak to peak. The output of the first stage is connected to the input of the second stage, and the second stage is connected to the input of the second stage.
A width of 100V to 200V is given from point 18 to point 19 in the figure. In total, this two-stage circuit has a peak-to-peak output of 2
Create a waveform of 00v.

Displacement time here means rise time or fall time. The rise times controlled by the present invention are the rise times of each stage, ie 0-100V in the first stage and 100-200V in the second stage. This rise time is 90 minutes from the maximum value of 10 in the waveform.
This is the time it takes to reach the highest level. Similarly, the descending time referred to in this application is the descending time of each stage, which is 10% from the 90th factor of the maximum amplitude value.
This is the time it takes to get involved.

The rising edge and the falling edge refer to the rising portion of the front end and the falling portion of the @ end, respectively. The rising edge is the portion of the waveform from the lowest point to the highest point, and the falling edge is the portion from the highest point to the lowest point. The rising edge has a positive slope, and the falling edge has a negative slope.

FIG. 6 is a schematic diagram of a circuit that controls the falling time of the switching waveform to a constant time. The power supply of VFET 26 is connected to ground potential, and the drain is connected to output terminal 28. When the base of transistor 25 is at a low potential, transistor 23 is turned on and drives the gate of VFET 26.
Turn on this device. When the base of transistor 250 goes high, it is turned on, and the base of transistor 26 is pulled to about ground potential, turning it off, removing the drive current to the gate of VFET 26, which is also turned off. switch 2
7 is a connection to the circuit shown in FIG. 8, which will be described later.

The current used to drive the gate of VFET 26 is obtained from a current source consisting of resistor 21 connected between a high voltage power supply Vs (eg 100V) and approximately ground potential. High voltage power supply V
Since the sO value often varies, the value of the current source also varies. The second terminal of the resistor 21 is connected to the base of the transistor 23, so that this terminal becomes higher than the ground potential by the sum of the base-emitter voltage of the transistor 230 and the transconductance gm of the VFET 2. If the gm of VFET26 changes, the voltage between the gate and source also changes.gm is the gain of VFET2 and includes a term that depends on the gate and source voltage.When the gate and source voltage changes, the voltage across the resistor 21 changes. As the current changes, so does the current.Compared to a high voltage source such as 1°Ov, this variation can be ignored.

The current from this current source is divided by the base of transistor 23 and capacitor 22. As output point 28 approaches ground, capacitor 22 draws more current from the base of transistor 26. In this way, capacitor 2
The current flowing through VFET 2 acts as a feedback control to regulate the amount of drive current sent to the gate of VFET 26. This feedback current is the direct current of the capacitor 22.
multiplied by the time rate of change of voltage, i.e. I=C
It's a toss.

The value C of capacitor 22 is constant. The supplied current is a function of the supply voltage VS and is Vs/R as Rfi fr-R of the resistor 21. Since the gain of transistor 26 is chosen to be very high, the value of the base current sent to transistor 26 is small compared to the current carried by capacitor 22. A shape that can be well approximated is one in which the current in the resistor 21 is equal to the current flowing in the capacitor 22. When replacing the current value of the resistor 21 in the above formula, Vs/R=C
− becomes.

t Here, if dv indicates the displacement in the entire range of Vs, then d
v=Vs and dt=Rxc. (ltf
, the rise time of the output voltage was set to a constant time independent of the voltage fluctuations experienced by the circuit.

FIG. 4 is a modified form of the fall time control circuit of FIG. 6, which includes a switching circuit 12 which receives digital logic signals from an external processor or the like via a terminal 31.

4.65 is the transistor 23 in Fig. 3.
．． 25, and the resistor 46 and capacitor 42 have the same function as the resistor 21 and capacitor 22. Since the gain of transistor 34 tends to be small, transistor 36 is added to boost its total gain.

In this manner, sufficient current is provided to the gate of VFET 30 to turn on the device.

The source of VFET 30 is output terminal 45.

A capacitor 44 and a resistor 46 having a power supply voltage VS are
A direct current source is created by dividing vs by the t direct of the resistor 46. In practice, the resistor 46 has one terminal connected to the capacitor 44 and the other terminal connected to the base of the transistor 66, which base becomes the voltage reference point of the resistor 46. Switch 29 is for connection to the circuit r+o, which will be explained later with respect to FIG.

The fourth switching circuit 12 consists of an inverter 62 and a transistor 33 connected in a common base format.
The source of VFET 30 floats when the device is not in use. This float is 0pol),! : VB volts, at which time the control circuit driving VFET 30 also floats. Therefore, digital logic signals must be transmitted across floating boundaries.

Although an inverter is used in this example, any logic gate may be used to receive a digital signal at input 31.

Transistor 33 acts as a switching current source to feed a digital logic signal (eg, a TTL level from ground) to a floating 29-hour control circuit. When a high level signal is applied to terminal 31 of inverter 62, transistor 6 turns on, which in turn turns off transistor 35 and transfers sufficient current in resistor 59 to transistor 34. Point at the base - turn on the device.

This ensures that the external drive current is V enough to turn on the device.
Applied to the gate of FET30.

FIG. 5 is a schematic diagram of a circuit that controls the falling edge of the switch waveform to a constant rate of change. The source of VFET 51 is connected to ground potential, and the drain serves as an output terminal 57. When transistor 550 base is held low, transistor 54 turns on, driving the gate of VFET 51 on, which turns on when transistor 550 base goes high. As a result, the base of the transistor 54 is pulled down to approximately the ground potential, the transistor 54 is turned off, and the drive current to the gate of the VFET 51 is eliminated. The rate of change dv is the change over time of the output voltage at the dt terminal 57;
The feedback current to the gate drive circuit of VFET 51 is equal to the total capacitor 56 divided by one. VFE
A driving current to T51 is given from a constant current source 52. The first line of the capacitor 56 is fixed. Since the current applied to the gate control circuit of VFET 51 is constant, the rate of change dv is constant t. This means that the falling edge of the output voltage, 11] and thus the holding voltage, is controlled at a constant rate of change. In this way, the falling edge is also fixed at a constant rate of change, and the output voltage IE
It maintains a constant slope even if the straightness changes. The increase in dv is offset by the increase in dt, and a constant L value is maintained.

In FIG. 6, a modification of the fifth falling edge control circuit includes a switching circuit 12 which receives a digital logic signal from an external processor or the like. Transistors 73.78 function similarly to transistors 54.55 of FIG.
Flow sufficient current to the gate of ET61 to turn it on. VF
The source of ET 61 is output terminal 62. The function of the switching circuit 12 in FIG. 6 is the same as that described in connection with FIG.

The circuit of FIG. 6 has a constant current source (Vcc) i different from the current source used in FIG. When transistor 78 turns on (keeps VFET61'5 off), VFET6
Since the source of the capacitor 68 is at ground, the capacitor 68 is charged to a DC level of Vc+ minus the potential drop of the diode 67.72 and the saturation voltage of the transistor 78. transistor 73
When turned on, the charge in capacitor 68 is driven by the emitter of transistor 73, and the current in resistor 69 is equal to Become direct. Since the base-emitter voltages of the transistors 3 and 77 are approximately equal, this is the voltage of the capacitor 68 divided by the voltage of the resistor 69. In this way a constant current source is created.

The circuit of FIG. 7 is a variation of the circuit of FIG. 6 and has a gate control isolation circuit that isolates the low voltage gate control circuit from the high voltage power supply. The drain of VFET 82 is output terminal 93. When switch 92 is in the vS position, diode 8
7 is reverse biased, with high voltage Vs and transistors 83.
84.85 and a current source consisting of a resistor 81 connected between the power supply Vs and the base of the transistor 84. At this time, it is desirable to turn off VFET 82, which requires ensuring that the gate of VFET 82 does not reach a voltage that would turn it on. The gate voltage of VFET 82 is the sum of the voltage at its source, the base-emitter voltage of transistor 89, and the voltage across resistor 91. Among these, the item that can be controlled is the voltage of the resistor 91.

By lowering the voltage across the low resistance of the resistor, VFET'
82'! It's nearly impossible to get it to about enough power to keep it off. Since diode 8B is reverse biased, the current in resistor 91 is almost entirely the base current of transistor 89. Since emitter current is the product of gain and base current, the voltage across resistor 91 is equal to
Emitter current x value of resistor 91 ÷ gain. If the gain of transistor 89 is made sufficiently large, its voltage can be kept at a low level without making the voltage of resistor 91 impossibly small.

When switch 92 is in the ground position, diode 87.8
8 becomes forward biased and transistor 89 turns off. At this time, this circuit works like the circuit shown in FIG.

FIG. 8 shows a drive system that provides a constant rise time from the peak to the holding voltage of peak IIf20[]'y. This system includes the circuits shown in FIGS. 6, 4, and 7.

Initially, circuit 110.130 is off and circuit 1201.1
40 is on. At this time, line 96 is pulled down to ground. Capacitor 940 has 100 volts across it and line 97 is at 100 volts.

Line 95, the output to the plasma cell, is at ground potential. When circuit 120 is off and circuit 110 is on, line 96 goes to 100 volts and line 97 of capacitor 94 goes up to 200 volts. line 9
7 provides the 200 volt power supply to circuit 160. Then,
Line 95 provides 100 volts to the cell. circuit 140
is off, and when circuit 130 is on, line 95 is 2
00pol) to the k cell. In this way, the circuit of FIG. 8 has a first stage that produces an output signal of 0 to 100 volts, and a second stage that produces an output signal of 0 to 100 volts with a reference value at the output of this stage. 0 to 20 on output line 95
Electricity 11' is generated based on the 0 volt ground and applied to the gas cell.

[Brief explanation of drawings]

FIG. 1 is a plan view of the plasma panel display driving device of the present invention, FIG. 2 is a diagram of waveforms obtained by the present invention,
6 to 8 are diagrams showing all embodiments of one circuit for controlling the rise or fall time of the plasma cell drive waveform of the present invention. 11... External processor, 12... Switching circuit, 13... Control circuit, 14... VFET
Output, 15...High pressure source, 16...Plasma se/lz. 22.44.53.68... Capacitor, 21.3
9.69.81.91...Resistance, 30,51.61
．． 82...VFET, 23.25.33.64.3
5.36.54.55.63.73.77.78.83
．． 84.85.89...transistor. Applicant: INTERTECIL BUSINESS MANMONS
Corporate/Yon Agent Patent Attorney Yamamoto
Jinro (1 other person) 1 Shi------11--------- FIG, I FIG 2 FIG, 4

Claims (1)

[Claims] A drive circuit that supplies a drive current to a plasma panel display device having a plasma cell, a VF, ET switch for supplying a pulse waveform voltage to the cell, and a power supply supplying a high voltage to the VFET switch; A control circuit that controls the displacement time of the pulse waveform voltage to be constant by a circuit that has a reference potential as the source potential of the VFET switch, and a control circuit that receives a digital logic signal and drives the control circuit to have a constant displacement time. A drive circuit similar to a switching device that supplies a pulse waveform voltage to the cell.