JPS596202U - Sequence control device - Google Patents

Sequence control device

Info

Publication number
JPS596202U
JPS596202U JP9930982U JP9930982U JPS596202U JP S596202 U JPS596202 U JP S596202U JP 9930982 U JP9930982 U JP 9930982U JP 9930982 U JP9930982 U JP 9930982U JP S596202 U JPS596202 U JP S596202U
Authority
JP
Japan
Prior art keywords
instruction
control device
sequence control
section
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9930982U
Other languages
Japanese (ja)
Inventor
押賀　孝幸
光祐 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9930982U priority Critical patent/JPS596202U/en
Publication of JPS596202U publication Critical patent/JPS596202U/en
Pending legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例を示すブロック図、第２図は本考案の一
実施例を示すブロック図である。 １：メモリー、２：プロセッサ、３．ＰＩｌｏ、　４：
パリティ−エラー検出回路、５：無効命令検出回路、６
：オアゲート、？、　　１１．　１２：アンドゲート、
８：制御対象、９ニブログラムカウンタ、１０：命令語
レジスタ、１３：エラー回数カウンタ。FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1: Memory, 2: Processor, 3. PIlo, 4:
Parity error detection circuit, 5: invalid instruction detection circuit, 6
:Orgate,? , 11. 12: And gate,
8: Controlled object, 9 Niprogram counter, 10: Instruction word register, 13: Error number counter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御内容を記憶した命令記憶部と、命令を実行するため
の演算部と、制御対象よりの入力信号と制御対象への出
力信号を演算部へ伝達する為の入出力部を有するシーケ
ンス制御装置において、前記命令記憶部より読み出した
命令が無効命令やパリティ−エラーとなるような異常命
令となった場合、その命令を無視して、再びその命令を
繰り返し読み出し、許容された回数の再読み出しまでに
正常な命令が読み出された場合には、これを演算して、
以後運転を続行し、再読み出しの回数を越えた場合には
、異常処理を行ない、運転を停止することを特徴とする
シーケンス制御装置。In a sequence control device that has an instruction storage section that stores control contents, an arithmetic section that executes the instructions, and an input/output section that transmits input signals from a controlled object and output signals to the controlled object to the arithmetic section. If the instruction read from the instruction storage unit is an invalid instruction or an abnormal instruction that causes a parity error, the instruction is ignored and the instruction is repeatedly read again until the number of times the instruction is reread is the allowed number of times. If a normal instruction is read, calculate this and
A sequence control device characterized in that if the operation continues thereafter and the number of times of re-reading is exceeded, abnormality processing is performed and the operation is stopped.
JP9930982U 1982-07-02 1982-07-02 Sequence control device Pending JPS596202U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9930982U JPS596202U (en) 1982-07-02 1982-07-02 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9930982U JPS596202U (en) 1982-07-02 1982-07-02 Sequence control device

Publications (1)

Publication Number Publication Date
JPS596202U true JPS596202U (en) 1984-01-14

Family

ID=30235402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9930982U Pending JPS596202U (en) 1982-07-02 1982-07-02 Sequence control device

Country Status (1)

Country Link
JP (1) JPS596202U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6341686A (en) * 1986-08-08 1988-02-22 Fuji Electric Co Ltd Operation controlling method for variable speed wafer feeding device
JPH08227315A (en) * 1995-10-27 1996-09-03 Hitachi Ltd Abnormal alarm device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6341686A (en) * 1986-08-08 1988-02-22 Fuji Electric Co Ltd Operation controlling method for variable speed wafer feeding device
JPH08227315A (en) * 1995-10-27 1996-09-03 Hitachi Ltd Abnormal alarm device

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