JPS596205U - load control device - Google Patents
load control deviceInfo
- Publication number
- JPS596205U JPS596205U JP9851582U JP9851582U JPS596205U JP S596205 U JPS596205 U JP S596205U JP 9851582 U JP9851582 U JP 9851582U JP 9851582 U JP9851582 U JP 9851582U JP S596205 U JPS596205 U JP S596205U
- Authority
- JP
- Japan
- Prior art keywords
- load
- controlled
- mark
- control device
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Voltage And Current In General (AREA)
- Remote Monitoring And Control Of Power-Distribution Networks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は一般的な照明負荷の集中ル制御装置のブロック
図、第2図は従来例のブロック図、第3図は同上に用い
るマークカードの正面図、第4図は同上に用いる親機の
正面図、第5図は同上に用いる親機の回路構成を示すブ
ロック図、第6図a。
bは同上の伝送信号を示す波形図、第7図は本考案の一
実施例のマークカードの要部正面図、第8図は本考案の
他の実施例のマークカードの要部拡大正面図、第9図は
同上の実施例における調光レベルの設定例の説明図であ
り、3は親機、4は照明負荷、9はカードリーグ、10
はマークカード、10aはタイミングマーク、11□、
11□・・・は制御データマーク部である。
乙=不一=ん
X′v
10o ’□
0oX10o 10゜Figure 1 is a block diagram of a general centralized control device for lighting loads, Figure 2 is a block diagram of a conventional example, Figure 3 is a front view of a mark card used in the same, and Figure 4 is a master unit used in the same. FIG. 5 is a front view of the same, and FIG. 5 is a block diagram showing the circuit configuration of the main unit used in the same, FIG. 6a. b is a waveform diagram showing the same transmission signal as above, FIG. 7 is a front view of the main part of a mark card according to one embodiment of the present invention, and FIG. 8 is an enlarged front view of the main part of a mark card according to another embodiment of the present invention. , FIG. 9 is an explanatory diagram of an example of setting the dimming level in the above embodiment, where 3 is the base unit, 4 is the lighting load, 9 is the card league, and 10
is a mark card, 10a is a timing mark, 11□,
11□... is a control data mark section. Otsu=Fuichi=nX'v 10o '□ 0oX10o 10゜
Claims (1)
た負荷制御装置を形成し、各被制御負荷の制御状態を設
定するためのマークカードを設けるとともに、このマー
クカードに記録された各被制御負荷毎の制御状態を読み
取って親機内の記憶部に入力するカード読取手段を設け
た負荷制御装置において、上記マークカード表面に被制
御負荷の配置状態を示す配置図を印刷し、この配置図上
の各被制御負荷配設位置に略対応する位置にその被制御
負荷の制御状態設定用の制御データマーク部を設けると
ともに、この制御データマーク部に対応して上記マーク
カードの側縁にマーク読取り制御用のタイミングマーク
を設けて成る負荷制御装置。A load control device is formed in which a large number of controlled loads are centrally controlled by a master unit, and a mark card is provided for setting the control state of each controlled load. In a load control device equipped with a card reading means for reading the control state of each controlled load and inputting it into a storage section in the master unit, a layout diagram showing the layout state of the controlled loads is printed on the surface of the mark card, and this layout diagram is printed on the surface of the mark card. A control data mark section for setting the control state of the controlled load is provided at a position approximately corresponding to each controlled load arrangement position above, and a mark is placed on the side edge of the mark card corresponding to this control data mark section. A load control device equipped with timing marks for read control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9851582U JPS596205U (en) | 1982-06-30 | 1982-06-30 | load control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9851582U JPS596205U (en) | 1982-06-30 | 1982-06-30 | load control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS596205U true JPS596205U (en) | 1984-01-14 |
| JPS635042Y2 JPS635042Y2 (en) | 1988-02-10 |
Family
ID=30233857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9851582U Granted JPS596205U (en) | 1982-06-30 | 1982-06-30 | load control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596205U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0553581U (en) * | 1991-12-24 | 1993-07-20 | 橋野 徹 | Retainer for sacred fire |
-
1982
- 1982-06-30 JP JP9851582U patent/JPS596205U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0553581U (en) * | 1991-12-24 | 1993-07-20 | 橋野 徹 | Retainer for sacred fire |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS635042Y2 (en) | 1988-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS596205U (en) | load control device | |
| JPS596206U (en) | load control device | |
| JPS58172981U (en) | display device | |
| JPS588972U (en) | printed wiring base material | |
| JPS5936269U (en) | Identification structure of printed wiring board | |
| JPS6112262U (en) | Ceramic substrate for printed wiring board | |
| JPS58189557U (en) | Printed circuit board with display mark for repair and inspection | |
| JPS5872873U (en) | soldering iron tip | |
| JPS619900U (en) | Check board for chip mounting board | |
| JPS59127260U (en) | printed circuit board | |
| JPS59104559U (en) | Multilayer printed circuit board with reference pattern | |
| JPS5877073U (en) | printed wiring board | |
| JPH0244377U (en) | ||
| JPS58120672U (en) | Printed board | |
| JPS6081670U (en) | printed wiring board | |
| JPS58116265U (en) | Printed board | |
| JPH022857U (en) | ||
| JPS6073273U (en) | Printed board | |
| JPS5846475U (en) | Circuit blocks for small electronic devices | |
| JPS5928748U (en) | data card | |
| JPS6081672U (en) | printed wiring board | |
| JPS585374U (en) | Board warping prevention mechanism | |
| JPS59185900U (en) | Element lead detection device | |
| JPS5961559U (en) | Printed card plug structure | |
| JPS60111060U (en) | Printed circuit board marking |