JPS596335U - solid state relay circuit - Google Patents

solid state relay circuit

Info

Publication number
JPS596335U
JPS596335U JP10095282U JP10095282U JPS596335U JP S596335 U JPS596335 U JP S596335U JP 10095282 U JP10095282 U JP 10095282U JP 10095282 U JP10095282 U JP 10095282U JP S596335 U JPS596335 U JP S596335U
Authority
JP
Japan
Prior art keywords
circuit
state relay
solid state
relay circuit
cyrisk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10095282U
Other languages
Japanese (ja)
Inventor
細呂木 隆夫
Original Assignee
和泉電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 和泉電気株式会社 filed Critical 和泉電気株式会社
Priority to JP10095282U priority Critical patent/JPS596335U/en
Publication of JPS596335U publication Critical patent/JPS596335U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの考案の一実施例に係るソリッドステートリレー
回路図である。 pl、 p2・・・フォトカプラ、Ql、Q2・・・フ
ォトトランジスタ、Q3・・・トランジスタ、Q4・・
・サイリスタ、B・・・ブリッジ整流器、L・・・負荷
、A・・・交流電源。
The figure is a solid state relay circuit diagram according to an embodiment of this invention. pl, p2...photocoupler, Ql, Q2...phototransistor, Q3...transistor, Q4...
・Thyristor, B...Bridge rectifier, L...Load, A...AC power supply.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ブリッジ整流器の整流端子間に入力回路とゼロクロス点
検出回路とサイリスクを接続し前記ブリッジ整流器の交
流端子間に交流電源と負荷との直列回路を接続して構成
し、前記入力回路およびゼロクロス点検出回路の両川力
信号の論理和信号により前記サイリスクを駆動して前記
負荷をオン・オフ制御するソリッドステートリレー回路
において、前記入力回路を2つのフォトトランジスタか
らなるフリップフロップ回路で構成したことを特徴とす
るソリッドステートリレー回路。
An input circuit, a zero-crossing point detection circuit, and Cyrisk are connected between the rectifying terminals of the bridge rectifier, and a series circuit of an AC power source and a load is connected between the AC terminals of the bridge rectifier, and the input circuit and the zero-crossing point detection circuit A solid-state relay circuit that controls the load on and off by driving the cyrisk with a logical sum signal of the Ryokawa power signals, characterized in that the input circuit is configured with a flip-flop circuit consisting of two phototransistors. solid state relay circuit.
JP10095282U 1982-07-02 1982-07-02 solid state relay circuit Pending JPS596335U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10095282U JPS596335U (en) 1982-07-02 1982-07-02 solid state relay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10095282U JPS596335U (en) 1982-07-02 1982-07-02 solid state relay circuit

Publications (1)

Publication Number Publication Date
JPS596335U true JPS596335U (en) 1984-01-17

Family

ID=30238598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10095282U Pending JPS596335U (en) 1982-07-02 1982-07-02 solid state relay circuit

Country Status (1)

Country Link
JP (1) JPS596335U (en)

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