JPS596343U - PLL tuner mute signal generator - Google Patents

PLL tuner mute signal generator

Info

Publication number
JPS596343U
JPS596343U JP10042682U JP10042682U JPS596343U JP S596343 U JPS596343 U JP S596343U JP 10042682 U JP10042682 U JP 10042682U JP 10042682 U JP10042682 U JP 10042682U JP S596343 U JPS596343 U JP S596343U
Authority
JP
Japan
Prior art keywords
signal generator
mute signal
division ratio
pll tuner
frequency division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10042682U
Other languages
Japanese (ja)
Other versions
JPS6314512Y2 (en
Inventor
幸弘 金子
秀樹 岩崎
黒崎　正謙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp filed Critical Pioneer Corp
Priority to JP10042682U priority Critical patent/JPS596343U/en
Publication of JPS596343U publication Critical patent/JPS596343U/en
Application granted granted Critical
Publication of JPS6314512Y2 publication Critical patent/JPS6314512Y2/ja
Granted legal-status Critical Current

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Landscapes

  • Superheterodyne Receivers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を示すブロック図、第２図は本考案の装
置を組み込んだチューナを示すブロック図、及び第３図
は本考案の要部の詳細を示すブロック図である。 ３ａ・・・シフトレジスタ（記憶手段）、８ａ・・・コ
ンパレータ（比較手段）、８Ｃ・・・ワンショットマル
チバイブレータ（パルス発生手段）。FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing a tuner incorporating the device of the present invention, and FIG. 3 is a block diagram showing details of the main parts of the present invention. 3a...Shift register (storage means), 8a...Comparator (comparison means), 8C...One-shot multivibrator (pulse generation means).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 現在受信中の周波数に対応する分周比データを記憶する
記憶手段と、この記憶手段に記憶されている前記分周比
データと、新しく受信しようとする周波数に対応する分
周比データとを比較して両分同化データが不一致のとき
信号を出力する比較手段と、この比較手段の出力信号に
応じてパルスを発生するパルス発生手段とを備えること
を特徴とするＰＬＬチューナのミュート信号発生装置。A storage means for storing frequency division ratio data corresponding to the frequency currently being received; and a comparison between the frequency division ratio data stored in this storage means and the frequency division ratio data corresponding to the frequency to be newly received. 1. A mute signal generating device for a PLL tuner, comprising: comparing means for outputting a signal when the two assimilated data do not match; and pulse generating means for generating a pulse in response to the output signal of the comparing means.
JP10042682U 1982-07-02 1982-07-02 PLL tuner mute signal generator Granted JPS596343U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10042682U JPS596343U (en) 1982-07-02 1982-07-02 PLL tuner mute signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10042682U JPS596343U (en) 1982-07-02 1982-07-02 PLL tuner mute signal generator

Publications (2)

Publication Number Publication Date
JPS596343U true JPS596343U (en) 1984-01-17
JPS6314512Y2 JPS6314512Y2 (en) 1988-04-22

Family

ID=30237575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10042682U Granted JPS596343U (en) 1982-07-02 1982-07-02 PLL tuner mute signal generator

Country Status (1)

Country Link
JP (1) JPS596343U (en)

Also Published As

Publication number Publication date
JPS6314512Y2 (en) 1988-04-22

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