JPS5963690U - full wave rectifier circuit - Google Patents
full wave rectifier circuitInfo
- Publication number
- JPS5963690U JPS5963690U JP15760982U JP15760982U JPS5963690U JP S5963690 U JPS5963690 U JP S5963690U JP 15760982 U JP15760982 U JP 15760982U JP 15760982 U JP15760982 U JP 15760982U JP S5963690 U JPS5963690 U JP S5963690U
- Authority
- JP
- Japan
- Prior art keywords
- rectifier circuit
- wave rectifier
- full wave
- resistor
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Rectifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の全波整流回路図、第2図は本考案からな
る実施例の全波整流回路図、第3図は電圧波形図、第4
図イ、用ま作用を説明するための等価回路図である。
1.6.10・・・オペアンプ(演算増幅器)、2゜3
.7〜9,11〜13・・・抵抗、4,5・・・ダイオ
ード。Fig. 1 is a conventional full-wave rectifier circuit diagram, Fig. 2 is a full-wave rectifier circuit diagram of an embodiment of the present invention, Fig. 3 is a voltage waveform diagram, and Fig. 4 is a diagram of a full-wave rectifier circuit according to an embodiment of the present invention.
Figure A is an equivalent circuit diagram for explaining the function. 1.6.10... operational amplifier (operational amplifier), 2゜3
.. 7-9, 11-13...resistance, 4,5...diode.
Claims (1)
端子TPが接地され、その反転入力端子TMが第1の抵
抗11を介して交流入力端子INに接続されると共に第
2の抵抗12を介して整流出力端子OUTに接続され、
更にその出力端子T0が第3の抵抗13を介して前記整
流出力端子OUTに接続されてなり、ぶつ前記第1、第
2及び第3の抵抗11,12.13の各抵抗値R,,R
2,R3が2対1対3の割合に設定されてなることを特
徴とする全波整流回路。An operational amplifier 10 operated by a power supply is provided, and its non-inverting input terminal TP is grounded, and its inverting input terminal TM is connected to an AC input terminal IN via a first resistor 11 and via a second resistor 12. is connected to the rectifier output terminal OUT,
Furthermore, its output terminal T0 is connected to the rectified output terminal OUT via a third resistor 13, and the respective resistance values R, , R of the first, second and third resistors 11, 12.
2. A full-wave rectifier circuit characterized in that R3 is set at a ratio of 2:1:3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15760982U JPS5963690U (en) | 1982-10-19 | 1982-10-19 | full wave rectifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15760982U JPS5963690U (en) | 1982-10-19 | 1982-10-19 | full wave rectifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5963690U true JPS5963690U (en) | 1984-04-26 |
| JPH0229462Y2 JPH0229462Y2 (en) | 1990-08-08 |
Family
ID=30347432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15760982U Granted JPS5963690U (en) | 1982-10-19 | 1982-10-19 | full wave rectifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5963690U (en) |
-
1982
- 1982-10-19 JP JP15760982U patent/JPS5963690U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0229462Y2 (en) | 1990-08-08 |
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