JPS596373U - 1H delay processing circuit - Google Patents
1H delay processing circuitInfo
- Publication number
- JPS596373U JPS596373U JP10020582U JP10020582U JPS596373U JP S596373 U JPS596373 U JP S596373U JP 10020582 U JP10020582 U JP 10020582U JP 10020582 U JP10020582 U JP 10020582U JP S596373 U JPS596373 U JP S596373U
- Authority
- JP
- Japan
- Prior art keywords
- processing circuit
- delay line
- chroma signal
- delay processing
- direct
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Processing Of Color Television Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のIH遅延装置を示す回路図、第2図はこ
の考案の一実施例を示す回路図である。
RA、 、RB、 RC,RD・・・抵抗、”A、’
”B”・・コイル、VRA・・・可変抵抗、21・・・
IH遅延線。FIG. 1 is a circuit diagram showing a conventional IH delay device, and FIG. 2 is a circuit diagram showing an embodiment of this invention. RA, ,RB, RC,RD...Resistance, "A,'
"B"...Coil, VRA...Variable resistance, 21...
IH delay line.
Claims (1)
イルと、マツチング用の可変抵抗とを並列接続し、前記
第1入力端子に入力クロマ信号を加え、前記第2入力端
子から分割抵抗を介してダイレクトクロマ信号をとり出
す構成とし、前記IH遅延線の挿入損失の大又は小に応
じて前記可変抵抗を調整することが、ダイレクトクロマ
信号レベルの小又は大となる相反する関係となるよう、
にしたことを特徴とするIH遅延処理回路。A matching coil and a matching variable resistor are connected in parallel between the first and second input terminals of the IH delay line, an input chroma signal is applied to the first input terminal, and a dividing resistor is connected from the second input terminal. The configuration is such that the direct chroma signal is extracted through the IH delay line, and adjusting the variable resistor depending on whether the insertion loss of the IH delay line is large or small creates a contradictory relationship in which the direct chroma signal level becomes small or large. Yo,
An IH delay processing circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10020582U JPS596373U (en) | 1982-07-02 | 1982-07-02 | 1H delay processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10020582U JPS596373U (en) | 1982-07-02 | 1982-07-02 | 1H delay processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS596373U true JPS596373U (en) | 1984-01-17 |
| JPS631508Y2 JPS631508Y2 (en) | 1988-01-14 |
Family
ID=30237151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10020582U Granted JPS596373U (en) | 1982-07-02 | 1982-07-02 | 1H delay processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596373U (en) |
-
1982
- 1982-07-02 JP JP10020582U patent/JPS596373U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS631508Y2 (en) | 1988-01-14 |
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