JPS5963764A - Manufacture of nonvolatile memory - Google Patents

Manufacture of nonvolatile memory

Info

Publication number
JPS5963764A
JPS5963764A JP57175033A JP17503382A JPS5963764A JP S5963764 A JPS5963764 A JP S5963764A JP 57175033 A JP57175033 A JP 57175033A JP 17503382 A JP17503382 A JP 17503382A JP S5963764 A JPS5963764 A JP S5963764A
Authority
JP
Japan
Prior art keywords
film
silicon dioxide
interface
nonvolatile memory
dioxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57175033A
Other languages
Japanese (ja)
Inventor
Kazuo Sato
和夫 佐藤
Ichizo Kamei
亀井 市蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP57175033A priority Critical patent/JPS5963764A/en
Publication of JPS5963764A publication Critical patent/JPS5963764A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To relax discontinuity, to reduce defects and strain and to stabilize the interface by forming an SiO2 thin-film on an Si substrate, nitriding the surface through treatment at a specific temperature in NH3 and vapor-growing an Si3N4 film up to predetermined thickness. CONSTITUTION:The SiO2 film 4 on an Si substrate 1 is bored and source and drain 3 are formed, and the opening is coated with the SiO2 thin-film 5 of approximately 25Angstrom . A thermally nitrided SiO2 film 8 is formed through treatment for thirty-five min at 700-1,000 deg.C in NH3, and the film 5 is further thinned. The film 5 is prepared in approximately 20Angstrom thickness, through which the film 5 can function as a tunnel medium, by selecting the conditions of growth of the film 5 and the conditins of NH3 treatment. When the Si3N4 film 6 is superposed through a vapor growth method, the defects and strain of the interface of the film 6 are reduced. An Al electrode 7 is formed, and the MNOS type nonvolatile memory is completed. According to the constitution, a threshold voltage value, memory holding characteristics, etc. hardly vary due to the defects and strain of the interface, and the nonvolatile memory can be manufactured with excellent accuracy.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、MNOS(金属−窒化シリコン膜−二酸化シ
リコン膜−半導体)型の不揮発性記憶装置の製造方法に
関し、電気的特性の揃ったMNO8型不揮発性記憶装置
の製造方法を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an MNOS (metal-silicon nitride film-silicon dioxide film-semiconductor) type nonvolatile memory device. The present invention provides a method for manufacturing a sexual memory device.

従来例の構成とその問題点 MNO8型不揮発性記憶装置は、窒化シリコン膜と薄い
二酸化シリコン膜の界面又は、その近傍の窒化シリコン
膜中に生じたトラップ準位に、半導体側から薄い二酸化
シリコン膜をトンネリングして注入、蓄積される電荷に
より電界効果トランジスタのしきい値電圧(Vth) 
 を変化させ、情報を記憶させるものであり、その記憶
保持特性を精度よく安定して揃えることが、MNO8型
不揮発性記憶装置の製造上の最大の課題であり、又実用
上の重大な問題となっている。
Conventional configuration and its problems The MNO8 type nonvolatile memory device has a thin silicon dioxide film applied from the semiconductor side to trap levels generated in the silicon nitride film at or near the interface between a silicon nitride film and a thin silicon dioxide film. The threshold voltage (Vth) of the field effect transistor increases due to the charge that is injected and accumulated by tunneling.
The most important challenge in manufacturing MNO8 type nonvolatile memory devices is to accurately and stably align the memory retention characteristics, and it is also a serious problem in practical use. It has become.

第1図は、従来から用いられているMNO’S型不揮発
性記憶装置の製造方法を説明する工程図である。まず、
第1図囚に示すようにシリコン基板1の表面部に、ソー
ス領域2.ドレイン領域3を選択拡散技術で形成し、選
択拡散時に形成される二酸化シリコン膜4の所定の部分
を、フォトエツチングで開孔した後、この間孔部分に、
電荷のトンネリングが起こりうるような厚さく約2o入
程度)の薄い二酸化シリコン膜5を700〜8oO℃の
酸素雰囲気中で酸化して形成する。
FIG. 1 is a process diagram illustrating a method of manufacturing a conventionally used MNO'S type nonvolatile memory device. first,
As shown in FIG. 1, a source region 2. After the drain region 3 is formed by selective diffusion technology and a predetermined portion of the silicon dioxide film 4 formed during the selective diffusion is opened by photoetching, a hole is formed in the hole portion.
A thin silicon dioxide film 5 having a thickness of approximately 200° C., which allows charge tunneling to occur, is oxidized in an oxygen atmosphere at a temperature of 700° to 800° C. to form the silicon dioxide film 5.

次いで、第1図の)に示すように、二酸化シリコン膜5
の上に、窒化シリコン膜6をシラン、又はジクロルシラ
ンとアンモニアとの混合気体からの熱分解で得られる、
いわゆる気相成長法により400〜SOO八程度の厚さ
に形成し、さらにその上に、アルミニウムのごとき金属
電極7を被着させる。
Next, as shown in FIG. 1), a silicon dioxide film 5 is formed.
A silicon nitride film 6 is formed on the silicon nitride film 6 by thermal decomposition from silane or a mixed gas of dichlorosilane and ammonia.
It is formed to a thickness of about 400 to SOO8 by a so-called vapor phase growth method, and then a metal electrode 7 such as aluminum is deposited thereon.

ところで、MNOS型不揮発性記憶装置は、その電気的
性質として、 (a)  ゲート印加電圧に対して、二酸化シリコン膜
と窒化シリコン膜の界面もしくは、その近傍の窒化シリ
コン中の電荷蓄積と非蓄積状態に対応するヒステリシス
曲線の上下の幅ΔVtb’(Lきい値電圧の窓の大きさ
)。
By the way, the electrical properties of the MNOS type nonvolatile memory device are as follows: (a) Charge accumulation and non-accumulation states in the silicon nitride at or near the interface between the silicon dioxide film and the silicon nitride film with respect to the gate applied voltage; The upper and lower widths of the hysteresis curve corresponding to ΔVtb' (the size of the L threshold voltage window).

(b)  蓄積、非蓄積状態の電荷の記憶保持特性。(b) Memory retention characteristics of charges in accumulated and non-accumulated states.

(c)  比較的高ゲート電圧を印加して、繰返し書き
込み消去を行なった後の上記(a)、 (b)項の劣化
特性。
(c) Deterioration characteristics in items (a) and (b) above after applying a relatively high gate voltage and repeatedly writing and erasing.

などの緒特性が、実用上きわめて重要であるが、このよ
うな特性は、次のような物性パラメータにより影響され
る。
These properties are extremely important in practice, and these properties are influenced by the following physical parameters.

(1)二酸化シリコン膜5の厚さ く2)電荷の蓄積されるトラップの分布(3)蓄積され
る電荷量 (4)窒化シリコン膜6の電気伝導度 (5)二酸化シリコン5一基板1界面及び、二酸化シリ
コン5−窒化シリコン6界面の状態上記物性パラメータ
は、二酸化シリコン膜5、及び窒化シリコン膜6の形成
条件によって著しく変化するもので、従来、その制御が
きわめて困難であり、精度よく安定した電気的特性をう
ろことがなかなかできないという大きな問題をかかえて
いた。特に、上述の従来例のように、二酸化シリコン膜
5の上に、窒化シリコン膜6を直接、気相成長法により
形成する方法では、二酸化シリコン膜5と窒化シリコン
膜、6の界面は、物性構造の異なる材料が機械的に接し
た不連続な面であり、この界面に歪や欠陥が発生するこ
とが多い。このような歪や欠陥は、上記の物性パラメー
タ中の(2)(6)項などに強く影響を与え、これが電
気的特性のそろったMNOS型不揮発性記憶装置を、精
度よ〈安定に製造することを実用上非常に困難にしてい
る。
(1) Thickness of silicon dioxide film 5 2) Distribution of traps where charge is accumulated (3) Amount of charge accumulated (4) Electrical conductivity of silicon nitride film 6 (5) Silicon dioxide 5 - substrate 1 interface and , the state of the silicon dioxide 5-silicon nitride 6 interface The physical parameters described above vary significantly depending on the formation conditions of the silicon dioxide film 5 and the silicon nitride film 6, and conventionally, it has been extremely difficult to control them, and it has been difficult to control them with precision and stability. The major problem was that it was difficult to determine the electrical characteristics. In particular, in the method of forming the silicon nitride film 6 directly on the silicon dioxide film 5 by vapor phase growth as in the conventional example described above, the interface between the silicon dioxide film 5 and the silicon nitride film 6 has physical properties. It is a discontinuous surface where materials with different structures come into mechanical contact, and distortions and defects often occur at this interface. Such distortions and defects strongly affect items (2) and (6) among the physical property parameters mentioned above, and this makes it difficult to manufacture MNOS nonvolatile memory devices with uniform electrical characteristics in a stable manner, rather than with precision. This makes it extremely difficult in practice.

本発明は、こうした従来の問題点を解消することを目的
としたもので、特に窒化シリコンと二酸化シリコン界面
状態の安定化に有効で、かつ、制御性・のよい不揮発性
記憶装置の製造方法を提供するものである。
The present invention aims to solve these conventional problems, and provides a method for manufacturing a nonvolatile memory device that is particularly effective in stabilizing the interface state between silicon nitride and silicon dioxide and has good controllability. This is what we provide.

発明の構成 本発明は、シリコン基板面上に、薄い二酸化シリコン膜
を形成後、アンモニアガス雰囲気中、700〜11oO
℃の高温で加熱を行ない、二酸化シリコン膜の表面を熱
窒化させ、その後、窒化シリコン膜を所定の厚さに気相
成長法により形成するもので、このことにより、二酸化
シリコン膜と窒化シリコン膜の界面を、熱窒化された二
酸化シリコン膜中にとりこみ、一種の不連続性を緩和し
、欠陥や歪を少なくすることを可能にしたものであるQ 実施例の説明 以下、本発明の詳細な説明する。第2図は、本発明の製
造方法を説明するだめの工程図である。
Structure of the Invention The present invention involves forming a thin silicon dioxide film on a silicon substrate surface, and then heating the film to 700 to 11oO in an ammonia gas atmosphere.
The surface of the silicon dioxide film is thermally nitrided by heating at a high temperature of °C, and then a silicon nitride film is formed to a predetermined thickness by vapor phase growth. By incorporating the interface into a thermally nitrided silicon dioxide film, it is possible to alleviate a kind of discontinuity and reduce defects and distortion. explain. FIG. 2 is a process diagram for explaining the manufacturing method of the present invention.

第2図(5)に示すごとく、シリコン基板1に、ソース
領域2.ドレイン領域3を周知の選択拡散技術で形成し
、選択拡散時に形成した二酸化シリコン膜4の所定の部
分をフォトエツチング後、との開孔部分に一例として2
5八程度の薄い二酸化シリコン膜5を形成させる。
As shown in FIG. 2(5), a source region 2. The drain region 3 is formed by a well-known selective diffusion technique, and after photo-etching a predetermined portion of the silicon dioxide film 4 formed during the selective diffusion, 2 is etched in the opening portion.
A silicon dioxide film 5 having a thickness of about 5.8 mm is formed.

次に、第2図(B)に示すよう尾、700〜1100℃
、アンモニアガス雰囲気中で30〜6分高温加熱を行な
い、二酸化シリコン膜5の表面を熱窒化させ、熱窒化二
酸化シリコン膜8を形成させる。
Next, as shown in Figure 2 (B), the tail was heated to 700-1100℃.
The surface of the silicon dioxide film 5 is thermally nitrided by heating at a high temperature for 30 to 6 minutes in an ammonia gas atmosphere to form a thermally nitrided silicon dioxide film 8.

この工程により、二酸化シリコン膜5の表面が窒化され
、二酸化シリコン膜5の厚さが薄くなる。
Through this step, the surface of the silicon dioxide film 5 is nitrided, and the thickness of the silicon dioxide film 5 is reduced.

従って、熱窒化後の二酸化シリコン膜5の厚さが、トン
ネリング媒体となりつる厚さく約20人種度)をうるよ
うに、二酸化シリコン膜の成長条件と、アンモニア処理
条件を制御する。
Therefore, the conditions for growing the silicon dioxide film and the conditions for the ammonia treatment are controlled so that the thickness of the silicon dioxide film 5 after thermal nitridation is approximately 20 degrees centigrade thick enough to serve as a tunneling medium.

次に、第2図(0に示すよって、熱窒化した二酸化シリ
コン膜8の上に、気相成長法により4o○〜80o八程
度0窒化シリコン膜6を形成する。
Next, as shown in FIG. 2 (0), on the thermally nitrided silicon dioxide film 8, a silicon nitride film 6 of approximately 4° to 80° is formed by vapor phase growth.

上述の工程により、従来の二酸化シリコン膜5と窒化シ
リコン膜6の界面の欠陥や歪が少なくなる。
Through the above-described steps, defects and distortions at the interface between the conventional silicon dioxide film 5 and silicon nitride film 6 are reduced.

さらに、第2図(0に示すように、窒化シリコン膜6上
にアルミニウム電極7を通常の真空蒸着法により被着さ
せる。
Further, as shown in FIG. 2 (0), an aluminum electrode 7 is deposited on the silicon nitride film 6 by a normal vacuum deposition method.

以上の如くして得られたMNO8型不揮発性記憶装置は
、熱窒化二酸化シリコン膜を形成するので、二酸化シリ
コン膜と窒化シリコン膜の界面の不連続性が解消され、
界面の欠陥や歪が少なくなり、その結果、欠陥や歪によ
り生じるMNO8型不揮発性記憶装置をしきい値電圧の
大きさ、記憶保持特性などの電気的特性のバラツキが少
なく、精度よく安定に製造することが容易になる。
Since the MNO8 type nonvolatile memory device obtained as described above forms a thermally nitrided silicon dioxide film, the discontinuity at the interface between the silicon dioxide film and the silicon nitride film is eliminated.
Defects and distortions at the interface are reduced, and as a result, MNO8 type nonvolatile memory devices produced by defects and distortions can be manufactured stably with high precision, with less variation in electrical properties such as threshold voltage and memory retention characteristics. It becomes easier to do.

本実施例では、ソース、ドレインを選択拡散で形成する
金属(アルミニウム)ゲート型のMNO8型不揮発性記
憶装置を作製する場合について説明を行なってきたが、
ゲート電極として、ポリシリコン等の高融点材料を用い
て、本発明の製造方法によりゲート絶縁膜を形成して、
周知のセルファライン技術により、ソース、ドレインを
形成してもよいことは言うまでもない。
In this example, a case has been described in which a metal (aluminum) gate type MNO8 type nonvolatile memory device in which the source and drain are formed by selective diffusion is manufactured.
A gate insulating film is formed by the manufacturing method of the present invention using a high melting point material such as polysilicon as a gate electrode,
It goes without saying that the source and drain may be formed using the well-known self-line technology.

発明の効果 以上のように、本発明は、MNO8型不揮発性記憶装置
のゲート絶縁膜を形成する際、トンネリング媒体となり
うるような薄い二酸化シリコン膜を形成後、アンモニア
ガス雰囲気中で高温加熱を行ない、二酸化シリコン膜の
表面を熱窒化させ、その後、気相成長法により窒化シリ
コン膜を所定の厚さに形成させることにより、二酸化シ
リコン膜と窒化シリコン膜の界面の不連続性をなくし、
界面の歪や欠陥を少なくさせることができる。その結果
、界面の歪や欠陥にもとすく、MNO8型不揮発性記憶
装置の電気的特性の不安定性を解消することができ、特
性のそろったMNO8型不揮発性記憶装置の精度のよい
安定した製造に大きく寄与するものである。
Effects of the Invention As described above, the present invention, when forming a gate insulating film of an MNO8 type nonvolatile memory device, forms a thin silicon dioxide film that can serve as a tunneling medium and then heats it at high temperature in an ammonia gas atmosphere. , by thermally nitriding the surface of the silicon dioxide film and then forming a silicon nitride film to a predetermined thickness by vapor phase growth, the discontinuity at the interface between the silicon dioxide film and the silicon nitride film is eliminated;
Distortion and defects at the interface can be reduced. As a result, it is possible to eliminate the instability of the electrical characteristics of the MNO8 nonvolatile memory device by reducing distortion and defects at the interface, and to ensure accurate and stable production of the MNO8 nonvolatile memory device with uniform characteristics. This will greatly contribute to the

【図面の簡単な説明】[Brief explanation of drawings]

第1図CAJω)は、従来のMNO8型不揮発性記憶装
置の製造工程断面図、第2図(3)〜(C)は、本発明
の製造工程断面図である。 1・・・・・・シリコン基板、6・・・・・・二酸化シ
リコン膜、6・・・・・・窒化シリコン膜、8・・・・
・・熱窒化した二酸化シリコン膜。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
FIG. 1 CAJω) is a sectional view of the manufacturing process of a conventional MNO8 type nonvolatile memory device, and FIGS. 2(3) to (C) are sectional views of the manufacturing process of the present invention. 1...Silicon substrate, 6...Silicon dioxide film, 6...Silicon nitride film, 8...
...Thermal nitrided silicon dioxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

【特許請求の範囲】[Claims] (1)−導電型半導体基板面に、所望厚の二酸化シリコ
ン膜を形成する工程と、アンモニアガス雰囲気中、7o
○〜11oo℃の温度で加熱し、前記二酸化シリコン膜
上に熱窒化二酸化シリコン膜を形成する工程と、前記熱
窒化二酸化シリコン膜上に窒化シリコン膜を形成する工
程を含むことを特徴とする不揮発性記憶装置の製造方法
(1) - Step of forming a silicon dioxide film of a desired thickness on the surface of a conductive type semiconductor substrate;
A nonvolatile method comprising the steps of heating at a temperature of ○ to 110° C. to form a thermally nitrided silicon dioxide film on the silicon dioxide film, and forming a silicon nitride film on the thermally nitrided silicon dioxide film. A method for producing a sexual memory device.
JP57175033A 1982-10-04 1982-10-04 Manufacture of nonvolatile memory Pending JPS5963764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57175033A JPS5963764A (en) 1982-10-04 1982-10-04 Manufacture of nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57175033A JPS5963764A (en) 1982-10-04 1982-10-04 Manufacture of nonvolatile memory

Publications (1)

Publication Number Publication Date
JPS5963764A true JPS5963764A (en) 1984-04-11

Family

ID=15989041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57175033A Pending JPS5963764A (en) 1982-10-04 1982-10-04 Manufacture of nonvolatile memory

Country Status (1)

Country Link
JP (1) JPS5963764A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US5506432A (en) * 1993-09-24 1996-04-09 Sony Corporation Metal nitride oxide semiconductor device
JP2002261175A (en) * 2000-12-28 2002-09-13 Sony Corp Nonvolatile semiconductor memory device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US5506432A (en) * 1993-09-24 1996-04-09 Sony Corporation Metal nitride oxide semiconductor device
JP2002261175A (en) * 2000-12-28 2002-09-13 Sony Corp Nonvolatile semiconductor memory device and method of manufacturing the same

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